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Intel
®
440GX AGPset Design Guide
3-35
Design Checklist
3.18.4 Wake On LAN (WOL) Header
•
A 3-pin WOL header interconnects the NIC and motherboard, and requires a 5VSB to pin1.
•
The WOL supports the MP_Wakeup pulse, allowing it to turn on the system via a signal pulse.
The LID input on the PIIX4E requires a 16ms debounce signal.
•
The MP_Wakeup signal, to the PIIX4E LID pin, requires a 5V to 3V translation. NOTE: The
LID pin will be configured as an active high signal through BIOS for this specific
implementation. If other logic is used for the 5V to 3V translation, make sure BIOS configures
the LID pin appropriately.
•
Maximum current provided by the power supply should be
no less than 600mA
.
•
BIOS support for boot-from-LAN (BIOS Boot Spec), if required.
•
See Wake on LAN* Leader Recommendations (order number 712940)
3.19 Software/BIOS
See the
Intel
®
Pentium
®
Pro Processor BIOS Writers Guide
for details regarding the following
responsibilities of the BIOS.
•
The Intel
®
Pentium
®
II processor L2 cache must be initialized and enabled by the BIOS.
•
The BIOS must load the BIOS Update to the Intel
®
Pentium
®
II processor as early as possible
in the POST during system boot up. The BIOS update signature mechanism should be used to
validate that the BIOS Update has been accepted by the processor.
•
It is recommended that the BIOS implement the minimum update API interface to allow the
BIOS Update stored in BIOS to be updated. Of the two Intel-defined update APIs, it is
recommended that the full real mode INT15h interface be implemented. An API calling utility
and test tool is available for this interface. Contact your local Intel Field Sales representative
for a copy.
•
Before starting a Flash update routine, use the MTRRs to disable caching, or only allow WT
mode. This prevents a WBINVD instruction from writing stale data to the Flash memory.
•
MTRR 6 & 7 must be left unprogrammed and are reserved for Operating System use.
3.19.1 USB and Multi-processor BIOS
•
Initialize the USB function properly in the PIIX4E component, if USB connectors are
provided.
•
Enable USB interrupt routing to one of the IRQ inputs. This should be set to Level Trigger
Mode.
•
When running Virtual-Wire mode, configure this through the I/O APIC. See page 3-10 of the
MultiProcessor Specification 1.4.
•
DP systems must construct an MPS table, see the
MultiProcessor Specification 1.4
for details.