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Intel
®
440GX AGPset Design Guide
3-7
Design Checklist
3.3.4 Uni-Processor (UP) Slot 1 Checklist
•
A UP system must connect BREQ0# of the Slot 1 connector to the 82443GX’s BREQ0#
signal. This will assign an agent ID of 0 to the processor. BREQ1# on the Slot 1 connector is
left as a no connect.
•
For a UP design, one set of GTL+ termination resistors (56 ohm) are recommended on the
motherboard (dual ended termination). The second set of terminations are provided on the
Intel
®
Pentium
®
II processor. Single ended termination (processor termination only) may be
achieved provided the trace lengths adhere to the very restrictive lengths given in the layout
guidelines.
•
FRCERR# may be left as a no connect for a UP design. On board termination resistors are not
required since they are provided on the Intel
®
Pentium
®
II processor.
3.3.5 Dual-Processor (DP) Slot 1 Checklist
•
A DP system must cross connect BREQ[1:0]# of the Slot 1 connector to the 82443GX’s
BREQ0# signal, i.e. BREQ0# should be tied to BREQ1# on the other processor.
•
No onboard termination is required because termination is provided on the Intel
®
Pentium
®
II
processor.
•
FRCERR# may be left as a no connect for a DP design if FRC mode is not supported. On
board termination resistors are not required since they are provided on the Intel
®
Pentium
®
II
processors.
•
Each processor site should have an isolated Vcc
CORE
power plane. Contact your VRM vendor
for availability of VRMs with current sharing capabilities if desired.
•
The SLOTOCC# signal can be used to block the system from booting if two sets of GTL+
termination resistors are not present. The Slot 1 VID lines from each of the connectors can be
used to determine if a non-functional processor core or terminator card is present.
•
The IOAPIC clock is T’d and distributed to the CPUs through 22 ohm series resistors.
3.3.6 Slot 1 Decoupling Capacitors
•
Additional Vcc
CORE
decoupling capacitance, high frequency or bulk, may be required for a
properly designed Slot 1 power delivery plane and VRM. For designs utilizing a local
regulator on the motherboard, adequate bulk decoupling is required. This bulk decoupling is
dependent upon the regulator reaction time. Contact your regulator vendor for bulk decoupling
recommendations that will meet the
VRM 8.2 DC-DC Converter Specification
.
•
Decoupling capacitor traces should be as short and wide as possible.
3.3.7 Voltage Regulator Module, VRM 8.2
•
Pin A5, formerly a reserved pin, is now 12VIN.
•
Pin B3, formerly a reserved pin, is now 5VIN.
•
ISHARE can be used in a DP design using the same manufacturer’s VRM to share the current
load between the two VRMs.
•
VRM 8.2 is modified from VRM 8.1 to provide up to 18A of ICC for future processors.
•
VID (voltage identification) pins from the processor will determine the Vcc
CORE
output of the
VRM.