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CDM-600 Satellite Modem Revision 7
Preface MN/CDM600.IOM
vi
7.2 Viterbi ..........................................................................................................................................7–1
7.3 Sequential.....................................................................................................................................7–2
7.4 Reed-Solomon Outer Codec.......................................................................................................7–3
7.5 Trellis Coding (FAST Option) ...................................................................................................7–5
7.6 Turbo Product Codec (Hardware Option) ...............................................................................7–6
7.7 TPC and Low Density Parity Check (LDPC) coding ..............................................................7–6
7.7.1 Introduction...........................................................................................................................7–6
7.7.2 LDPC versus TPC.................................................................................................................7–7
7.7.3 End-to-End Processing Delay ...............................................................................................7–9
7.8 Uncoded Operation (No FEC) .................................................................................................7–11
CHAPTER 8. OFFSET QPSK OPERATION.........................................................................8–1
CHAPTER 9. OPEN NETWORK OPERATIONS ..................................................................9–1
9.1 Introduction.................................................................................................................................9–1
9.2 IBS................................................................................................................................................9–1
9.2.1 IBS Clock/data recovery and De-jitter..................................................................................9–2
9.2.2 IBS Framing..........................................................................................................................9–2
9.2.3 IBS Engineering Service Channel.........................................................................................9–2
9.2.4 IBS Scrambling.....................................................................................................................9–2
9.3 Drop and Insert...........................................................................................................................9–2
9.3.1 D&I Primary Data Interfaces ................................................................................................9–3
9.3.2 D&I Framing.........................................................................................................................9–3
9.4 IDR ...............................................................................................................................................9–4
9.4.1 IDR Primary Data Interfaces.................................................................................................9–5
9.4.2 IDR Engineering Service Channel........................................................................................9–5
CHAPTER 10. CLOCK MODES AND DROP AND INSERT (D&I) ....................................10–1
10.1 Transmit Clocking ....................................................................................................................10–1
10.1.1 Internal Clock......................................................................................................................10–1
10.1.2 Tx Terrestrial ......................................................................................................................10–2
10.1.3 Rx Loop-Timed, RX=TX....................................................................................................10–2
10.1.4 Rx Loop-Timed, RX<>TX (Asymmetric Loop Timing)....................................................10–2
10.1.5 External Clock ....................................................................................................................10–2
10.2 Receive Clocking.......................................................................................................................10–3
10.2.1 Buffer Disabled (RX Satellite)............................................................................................10–3
10.2.2 Buffer Enabled, TX=RX (TX Terrestrial or External Clock).............................................10–3