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2.7.2.4ExampleofMDIORegisterAccessCode
PeripheralArchitecture
TheMDIOmoduleusestheMDIOuseraccessregister(USERACCESSn)toaccessthePHYcontrol
registers.Softwarefunctionsthatimplementtheaccessprocessmaysimplybethefollowingfourmacros:
•PHYREG_read(regadr,phyadr)StarttheprocessofreadingaPHYregister
•PHYREG_write(regadr,phyadr,data)StarttheprocessofwritingaPHYregister
•PHYREG_wait()Synchronizeoperation(makesureread/writeisidle)
•PHYREG_waitResults(results)Waitforreadtocompleteandreturndataread
Notethatitisnotnecessarytowaitafterawriteoperation,aslongasthestatusischeckedbeforeevery
operationtomakesuretheMDIOhardwareisidle.AnalternativeapproachistocallPHYREG_wait()after
everywrite,andPHYREG_waitResults()aftereveryread,thenthehardwarecanbeassumedtobeidle
whenstartinganewoperation.
Theimplementationofthesemacrosusingthechipsupportlibrary(CSL)isshowninExample3
(USERACCESS0isassumed).
NotethatthisimplementationdoesnotchecktheACKbitinUSERACCESSnonPHYregisterreads(does
notfollowtheprocedureoutlinedinSection2.7.2.3).SincetheMDIOPHYalivestatusregister(ALIVE)is
usedtoinitiallyselectaPHY,itisassumedthatthePHYisacknowledgingreadoperations.Itispossible
thataPHYcouldbecomeinactiveatafuturepointintime.AnexampleofthiswouldbeaPHYthatcan
haveitsMDIOaddresseschangedwhilethesystemisrunning.Itisnotverylikely,butthisconditioncan
betestedbyperiodicallycheckingthePHYstateinALIVE.
Example3.MDIORegisterAccessMacros
#definePHYREG_read(regadr,phyadr)
MDIO_REGS->USERACCESS0=
CSL_FMK(MDIO_USERACCESS0_GO,1u)|/
CSL_FMK(MDIO_USERACCESS0_REGADR,regadr)|/
CSL_FMK(MDIO_USERACCESS0_PHYADR,phyadr)
#definePHYREG_write(regadr,phyadr,data)
MDIO_REGS->USERACCESS0=
CSL_FMK(MDIO_USERACCESS0_GO,1u)|/
CSL_FMK(MDIO_USERACCESS0_WRITE,1)|/
CSL_FMK(MDIO_USERACCESS0_REGADR,regadr)|/
CSL_FMK(MDIO_USERACCESS0_PHYADR,phyadr)|/
CSL_FMK(MDIO_USERACCESS0_DATA,data)
#definePHYREG_wait()
while(CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO))
#definePHYREG_waitResults(results){
while(CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO));
results=CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_DATA);}
EthernetMediaAccessController(EMAC)/ 32SPRU941A–April2007
ManagementDataInput/Output(MDIO)
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