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5EthernetMediaAccessController(EMAC)Registers
EthernetMediaAccessController(EMAC)Registers
Table25liststhememory-mappedregistersfortheEMAC.Seethedevice-specificdatamanualforthe
memoryaddressoftheseregisters.
Table25.EthernetMediaAccessController(EMAC)Registers
OffsetAcronymRegisterDescriptionSection
0hTXIDVERTransmitIdentificationandVersionRegisterSection5.1
4hTXCONTROLTransmitControlRegisterSection5.2
8hTXTEARDOWNTransmitTeardownRegisterSection5.3
10hRXIDVERReceiveIdentificationandVersionRegisterSection5.4
14hRXCONTROLReceiveControlRegisterSection5.5
18hRXTEARDOWNReceiveTeardownRegisterSection5.6
80hTXINTSTATRAWTransmitInterruptStatus(Unmasked)RegisterSection5.7
84hTXINTSTATMASKEDTransmitInterruptStatus(Masked)RegisterSection5.8
88hTXINTMASKSETTransmitInterruptMaskSetRegisterSection5.9
8ChTXINTMASKCLEARTransmitInterruptClearRegisterSection5.10
90hMACINVECTORMACInputVectorRegisterSection5.11
A0hRXINTSTATRAWReceiveInterruptStatus(Unmasked)RegisterSection5.12
A4hRXINTSTATMASKEDReceiveInterruptStatus(Masked)RegisterSection5.13
A8hRXINTMASKSETReceiveInterruptMaskSetRegisterSection5.14
AChRXINTMASKCLEARReceiveInterruptMaskClearRegisterSection5.15
B0hMACINTSTATRAWMACInterruptStatus(Unmasked)RegisterSection5.16
B4hMACINTSTATMASKEDMACInterruptStatus(Masked)RegisterSection5.17
B8hMACINTMASKSETMACInterruptMaskSetRegisterSection5.18
BChMACINTMASKCLEARMACInterruptMaskClearRegisterSection5.19
100hRXMBPENABLEReceiveMulticast/Broadcast/PromiscuousChannelEnableRegisterSection5.20
104hRXUNICASTSETReceiveUnicastEnableSetRegisterSection5.21
108hRXUNICASTCLEARReceiveUnicastClearRegisterSection5.22
10ChRXMAXLENReceiveMaximumLengthRegisterSection5.23
110hRXBUFFEROFFSETReceiveBufferOffsetRegisterSection5.24
114hRXFILTERLOWTHRESHReceiveFilterLowPriorityFrameThresholdRegisterSection5.25
120hRX0FLOWTHRESHReceiveChannel0FlowControlThresholdRegisterSection5.26
124hRX1FLOWTHRESHReceiveChannel1FlowControlThresholdRegisterSection5.26
128hRX2FLOWTHRESHReceiveChannel2FlowControlThresholdRegisterSection5.26
12ChRX3FLOWTHRESHReceiveChannel3FlowControlThresholdRegisterSection5.26
130hRX4FLOWTHRESHReceiveChannel4FlowControlThresholdRegisterSection5.26
134hRX5FLOWTHRESHReceiveChannel5FlowControlThresholdRegisterSection5.26
138hRX6FLOWTHRESHReceiveChannel6FlowControlThresholdRegisterSection5.26
13ChRX7FLOWTHRESHReceiveChannel7FlowControlThresholdRegisterSection5.26
140hRX0FREEBUFFERReceiveChannel0FreeBufferCountRegisterSection5.27
144hRX1FREEBUFFERReceiveChannel1FreeBufferCountRegisterSection5.27
148hRX2FREEBUFFERReceiveChannel2FreeBufferCountRegisterSection5.27
14ChRX3FREEBUFFERReceiveChannel3FreeBufferCountRegisterSection5.27
150hRX4FREEBUFFERReceiveChannel4FreeBufferCountRegisterSection5.27
154hRX5FREEBUFFERReceiveChannel5FreeBufferCountRegisterSection5.27
158hRX6FREEBUFFERReceiveChannel6FreeBufferCountRegisterSection5.27
15ChRX7FREEBUFFERReceiveChannel7FreeBufferCountRegisterSection5.27
160hMACCONTROLMACControlRegisterSection5.28
164hMACSTATUSMACStatusRegisterSection5.29
68EthernetMediaAccessController(EMAC)/SPRU941A–April2007
ManagementDataInput/Output(MDIO)
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