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5.22ReceiveUnicastClearRegister(RXUNICASTCLEAR)
EthernetMediaAccessController(EMAC)Registers
Thereceiveunicastclearregister(RXUNICASTCLEAR)isshowninFigure48anddescribedin
Table47.
Figure48.ReceiveUnicastClearRegister(RXUNICASTCLEAR)
3116
Reserved
R-0
158
Reserved
R-0
76543210
RXCH7ENRXCH6ENRXCH5ENRXCH4ENRXCH3ENRXCH2ENRXCH1ENRXCH0EN
R/WC-0R/WC-0R/WC-0R/WC-0R/WC-0R/WC-0R/WC-0R/WC-0
LEGEND:R=Readonly;R/W=Read/Write;WC=Write1toclear,writeof0hasnoeffect;-n=valueafterreset
Table47.ReceiveUnicastClearRegister(RXUNICASTCLEAR)FieldDescriptions
BitFieldValueDescription
31-8Reserved0Reserved
7RXCH7EN0-1Receivechannel7unicastenableclearbit.Write1tocleartheenable,awriteof0hasnoeffect.
6RXCH6EN0-1Receivechannel6unicastenableclearbit.Write1tocleartheenable,awriteof0hasnoeffect.
5RXCH5EN0-1Receivechannel5unicastenableclearbit.Write1tocleartheenable,awriteof0hasnoeffect.
4RXCH4EN0-1Receivechannel4unicastenableclearbit.Write1tocleartheenable,awriteof0hasnoeffect.
3RXCH3EN0-1Receivechannel3unicastenableclearbit.Write1tocleartheenable,awriteof0hasnoeffect.
2RXCH2EN0-1Receivechannel2unicastenableclearbit.Write1tocleartheenable,awriteof0hasnoeffect.
1RXCH1EN0-1Receivechannel1unicastenableclearbit.Write1tocleartheenable,awriteof0hasnoeffect.
0RXCH0EN0-1Receivechannel0unicastenableclearbit.Write1tocleartheenable,awriteof0hasnoeffect.
90EthernetMediaAccessController(EMAC)/SPRU941A–April2007
ManagementDataInput/Output(MDIO)
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