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3EMACControlModuleRegisters
3.1EMACControlModuleInterruptControlRegister(EWCTL)
EMACControlModuleRegisters
Table7liststhememory-mappedregistersfortheEMACcontrolmodule.Seethedevice-specificdata
manualforthememoryaddressoftheseregisters.
Table7.EMACControlModuleRegisters
OffsetAcronymRegisterDescriptionSection
04hEWCTLEMACControlModuleInterruptControlRegisterSection3.1
08hEWINTTCNTEMACControlModuleInterruptTimerCountRegisterSection3.2
TheEMACcontrolmoduleinterruptcontrolregister(EWCTL)isusedtoenableanddisablethecentral
interruptfromtheEMACandMDIOmodules.
ItisexpectedthatanytimetheEMACandMDIOinterruptisbeingserviced,thesoftwaredisablesthe
INTENbitinEWCTL.Thisensuresthattheinterruptlinegoesbacktozero.Thesoftwarere-enables
theINTENbitafterclearingallthependinginterruptsandbeforeleavingtheinterruptserviceroutine.At
thispoint,iftheEMACcontrolmodulemonitorsanyinterruptsstillpending,itreassertstheinterrupt
line,andgeneratesanewedgethattheCPUcanrecognize.
AnytimetheINTENbitisclearedto0,theEMAC_MDIO_INTsignaltotheCPUiskeptdeasserted.If
theINTENbitissetto1,thentheinterruptcontrollogicchecksalltheinterruptlinesfromEMACand
MDIO.Ifanyoftheseinterruptlinesareactive,theEMAC_MDIO_INTsignalisasserted.Assertionof
thissignalgeneratesanedge,whichcanthenberecognizedasavalidinterruptbytheCPU.
TheINTENbittakescareoftwoproblemsassociatedwithlevelinterruptsfromtheEMACandthe
MDIOmodules.First,itmakessurethatnoneoftheinterruptsaremissed;second,itmakessurethat
onlytherequirednumberofinterruptsaresenttotheCPU.
TheEWCTLisshowninFigure11anddescribedinTable8.
Figure11.EMACControlModuleInterruptControlRegister(EWCTL)
3116
Reserved
R-0
1510
ReservedINTEN
R-0R/W-0
LEGEND:R=Readonly;R/W=Read/Write;-n=valueafterreset
Table8.EMACControlModuleInterruptControlRegister(EWCTL)FieldDescriptions
BitFieldValueDescription
31-1Reserved0Reserved
0INTENControlstheEMAC_MDIO_INTinterruptgenerationtotheCPU.
0EMACandMDIOinterruptsaredisabled.
1EMACandMDIOinterruptsareenabled.
SPRU941A–April2007EthernetMediaAccessController(EMAC)/53
ManagementDataInput/Output(MDIO)
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