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4.2MDIOControlRegister(CONTROL)
MDIORegisters
TheMDIOcontrolregister(CONTROL)isshowninFigure14anddescribedinTable12.
Figure14.MDIOControlRegister(CONTROL)
313029282423212019181716
IDLEENABLERsvdHIGHEST_USER_CHANNELReservedPREAMBLEFAULTFAULTENBReserved
R-1R/W-0R-0R-1R-0R/W-0R/WC-0R/W-0R-0
150
CLKDIV
R/W-FFh
LEGEND:R/W=R=Readonly;R/W=Read/Write;WC=Write1toclear;-n=valueafterreset
Table12.MDIOControlRegister(CONTROL)FieldDescriptions
BitFieldValueDescription
31IDLEStatemachineIDLEstatusbit.
0Statemachineisnotinidlestate.
1Statemachineisinidlestate.
30ENABLEStatemachineenablecontrolbit.IftheMDIOstatemachineisactiveatthetimeitis
disabled,itwillcompletethecurrentoperationbeforehaltingandsettingtheidlebit.
0DisablestheMDIOstatemachine.
1EnabletheMDIOstatemachine.
29Reserved0Reserved
28-24HIGHEST_USER_CHANNEL0-1FhHighestuserchannelthatisavailableinthemodule.Itiscurrentlysetto1.This
impliesthatMDIOUserAccess1isthehighestavailableuseraccesschannel.
23-21Reserved0Reserved
20PREAMBLEPreambledisable
0StandardMDIOpreambleisused.
1DisablesthisdevicefromsendingMDIOframepreambles.
19FAULTFaultindicator.Thisbitissetto1iftheMDIOpinsfailtoreadbackwhatthedevice
isdrivingontothem.Thisindicatesaphysicallayerfaultandthemodulestate
machineisreset.Writinga1toitclearsthisbit.
0Nofailure
1Physicallayerfault;theMDIOstatemachineisreset.
18FAULTENBFaultdetectenable.Thisbithastobesetto1toenablethephysicallayerfault
detection.
0Disablesthephysicallayerfaultdetection.
1Enablesthephysicallayerfaultdetection.
17-16Reserved0Reserved
15-0CLKDIV0-FFFFhClockDividerbits.Thisfieldspecifiesthedivisionratiobetweentheperipheralclock
andthefrequencyofMDCLK.MDCLKisdisabledwhenCLKDIVisclearedto0.
MDCLKfrequency=peripheralclockfrequency/(CLKDIV+1).
56EthernetMediaAccessController(EMAC)/SPRU941A–April2007
ManagementDataInput/Output(MDIO)
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