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2.16.2MDIOModuleInterruptEventsandRequests
2.16.2.1LinkChangeInterrupt
2.16.2.2UserAccessCompletionInterrupt
2.16.3ProperInterruptProcessing
2.16.4InterruptMultiplexing
PeripheralArchitecture
TheMDIOmodulegeneratestwointerruptevents:
•LINKINT:Serialinterfacelinkchangeinterrupt.IndicatesachangeinthestateofthePHYlink
•USERINT:Serialinterfaceusercommandeventcompleteinterrupt
TheMDIOmoduleassertsalinkchangeinterrupt(LINKINT)ifthereisachangeinthelinkstateofthe
PHYcorrespondingtotheaddressinthePHYADRMONbitintheMDIOuserPHYselectregistern
(USERPHYSELn),andiftheLINKINTENBbitisalsosetinUSERPHYSELn.Thisinterrupteventisalso
capturedintheLINKINTRAWbitintheMDIOlinkstatuschangeinterruptregister(LINKINTRAW).
LINKINTRAWbits0and1correspondtoUSERPHYSEL0andUSERPHYSEL1,respectively.
Whentheinterruptisenabledandgenerated,thecorrespondingLINKINTMASKEDbitisalsosetinthe
MDIOlinkstatuschangeinterruptregister(LINKINTMASKED).Theinterruptisclearedbywritingback
thesamebittoLINKINTMASKED(writetoclear).
WhentheGObitinoneoftheMDIOuseraccessregisters(USERACCESSn)transitionsfrom1to0
(indicatingcompletionofauseraccess)andthecorrespondingUSERINTMASKSETbitintheMDIO
usercommandcompleteinterruptmasksetregister(USERINTMASKSET)correspondingto
USERACCESS0orUSERACCESS1isset,auseraccesscompletioninterrupt(USERINT)isasserted.
ThisinterrupteventisalsocapturedintheUSERINTRAWbitintheMDIOusercommandcomplete
interruptregister(USERINTRAW).USERINTRAWbits0andbit1correspondtoUSERACCESS0and
USERACCESS1,respectively.
Whentheinterruptisenabledandgenerated,thecorrespondingUSERINTMASKEDbitisalsosetin
theMDIOusercommandcompleteinterruptregister(USERINTMASKED).Theinterruptisclearedby
writingbackthesamebittoUSERINTMASKED(writetoclear).
AlltheinterruptssignaledfromtheEMACandMDIOmodulesareleveldriven,soiftheyremainactive,
theirlevelremainsconstant;theCPUcorerequiresedge-triggeredinterrupts.Inordertoproperly
convertthelevel-driveninterruptsignaltoanedge-triggeredsignal,theapplicationsoftwaremustmake
useoftheinterruptcontrollogiccontainedintheEMACcontrolmodule.
Section2.6.3discussestheinterruptcontrolcontainedintheEMACcontrolmodule.Forsafeinterrupt
processing,uponentrytotheISR,thesoftwareapplicationshoulddisableinterruptsusingtheEMAC
controlmoduleinterruptcontrolregister(EWCTL),andthenreenablethemuponleavingtheISR.Ifany
interruptsignalsareactiveatthattime,thiscreatesanotherrisingedgeontheinterruptsignalgoingto
theCPUinterruptcontroller,thustriggeringanotherinterrupt.TheEMACcontrolmodulealsousesthe
EMACcontrolmoduleinterrupttimercountregister(EWINTTCNT)toimplementinterruptpacing.
TheEMACcontrolmodulecombinesdifferentinterruptsignalsfromboththeEMACandMDIOmodules
andgeneratesasingleinterruptsignalthatiswiredtotheCPUinterruptcontroller.Oncethisinterruptis
generated,thereasonfortheinterruptcanbereadfromtheMACinputvectorregister
(MACINVECTOR)locatedintheEMACmemorymap.MACINVECTORcombinesthestatusofthe
following20interruptsignals:TXPENDn,RXPENDn,STATPEND,HOSTPEND,LINKINT,and
USERINT.
TheEMACandMDIOinterruptsarecombinedwithintheEMACcontrolmoduleandmappedtothe
DSPinterruptINT43throughtheDSPinterruptcontroller.FormoredetailsontheDSPinterrupt
controller,seetheTMS320C64x+DSPMegamoduleReferenceGuide(SPRU871).
SPRU941A–April2007EthernetMediaAccessController(EMAC)/51
ManagementDataInput/Output(MDIO)
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