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2.16InterruptSupport
2.16.1EMACModuleInterruptEventsandRequests
2.16.1.1TransmitPacketCompletionInterrupts
2.16.1.2ReceivePacketCompletionInterrupts
PeripheralArchitecture
TheEMACmodulegenerates18interruptevents:
•TXPENDn:Transmitpacketcompletioninterruptfortransmitchannels0through7
•RXPENDn:Receivepacketcompletioninterruptforreceivechannels0through7
•STATPEND:Statisticsinterrupt
•HOSTPEND:Hosterrorinterrupt
ThetransmitDMAenginehaseightchannels,witheachchannelhavingacorrespondinginterrupt
(TXPENDn).ThetransmitinterruptsarelevelinterruptsthatremainasserteduntilclearedbytheCPU.
Eachoftheeighttransmitchannelinterruptsmaybeindividuallyenabledbysettingtheappropriatebit
inthetransmitinterruptmasksetregister(TXINTMASKSET)to1.Eachoftheeighttransmitchannel
interruptsmaybeindividuallydisabledbyclearingtheappropriatebitinthetransmitinterruptmask
clearregister(TXINTMASKCLEAR)to0.Therawandmaskedtransmitinterruptstatusmaybereadby
readingthetransmitinterruptstatus(unmasked)register(TXINTSTATRAW)andthetransmitinterrupt
status(masked)register(TXINTSTATMASKED),respectively.
WhentheEMACcompletesthetransmissionofapacket,theEMACissuesaninterrupttotheCPUby
writingthepacket’slastbufferdescriptoraddresstotheappropriatechannelqueue’stransmit
completionpointerlocatedinthestateRAMblock.Theinterruptisgeneratedbythewritewhen
enabledbytheinterruptmask,regardlessofthevaluewritten.
Uponinterruptreception,theCPUprocessesoneormorepacketsfromthebufferchainandthen
acknowledgesaninterruptbywritingtheaddressofthelastbufferdescriptorprocessedtothequeue’s
associatedtransmitcompletionpointerinthetransmitDMAstateRAM.
Thedatawrittenbythehost(bufferdescriptoraddressofthelastprocessedbuffer)iscomparedtothe
dataintheregisterwrittenbytheEMACport(addressoflastbufferdescriptorusedbytheEMAC).If
thetwovaluesarenotequal(whichmeansthattheEMAChastransmittedmorepacketsthantheCPU
hasprocessedinterruptsfor),thetransmitpacketcompletioninterruptsignalremainsasserted.Ifthe
twovaluesareequal(whichmeansthatthehosthasprocessedallpacketsthattheEMAChas
transferred),thependinginterruptiscleared.ThevaluethattheEMACisexpectingisfoundbyreading
thetransmitchannelncompletionpointerregister(TXnCP).
TheEMACwritetothecompletionpointeractuallystoresthevalueinthestateRAM.TheCPUwritten
valuedoesnotactuallychangetheregistervalue.Thehostwrittenvalueiscomparedtotheregister
content(whichwaswrittenbytheEMAC)andifthetwovaluesareequalthentheinterruptisremoved;
otherwise,theinterruptremainsasserted.Thehostmayprocessmultiplepacketspriorto
acknowledginganinterrupt,orthehostmayacknowledgeinterruptsforeverypacket.
ThereceiveDMAenginehaseightchannels,whicheachchannelhavingacorrespondinginterrupt
(RXPENDn).ThereceiveinterruptsarelevelinterruptsthatremainasserteduntilclearedbytheCPU.
Eachoftheeightreceivechannelinterruptsmaybeindividuallyenabledbysettingtheappropriatebitin
thereceiveinterruptmasksetregister(RXINTMASKSET)to1.Eachoftheeightreceivechannel
interruptsmaybeindividuallydisabledbyclearingtheappropriatebitinthereceiveinterruptmaskclear
register(RXINTMASKCLEAR)to0.Therawandmaskedreceiveinterruptstatusmaybereadby
readingthereceiveinterruptstatus(unmasked)register(RXINTSTATRAW)andthereceiveinterrupt
status(masked)register(RXINTSTATMASKED),respectively.
WhentheEMACcompletesapacketreception,theEMACissuesaninterrupttotheCPUbywritingthe
packet'slastbufferdescriptoraddresstotheappropriatechannelqueue'sreceivecompletionpointer
locatedinthestateRAMblock.Theinterruptisgeneratedbythewritewhenenabledbytheinterrupt
mask,regardlessofthevaluewritten.
SPRU941A–April2007EthernetMediaAccessController(EMAC)/49
ManagementDataInput/Output(MDIO)
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