Filter
Top Products
www.ti.com
2.8.1.4TransmitDMAEngine
2.8.1.5TransmitFIFO
2.8.1.6MACTransmitter
2.8.1.7StatisticsLogic
2.8.1.8StateRAM
2.8.1.9EMACInterruptController
2.8.1.10ControlRegistersandLogic
2.8.1.11ClockandResetLogic
2.8.2EMACModuleOperationalOverview
PeripheralArchitecture
ThetransmitDMAengineistheinterfacebetweenthetransmitFIFOandtheCPU.Itinterfacestothe
CPUthroughthebusarbiterintheEMACcontrolmodule.
ThetransmitFIFOconsistsofthreecellsof64–byteseachandassociatedcontrollogic.TheFIFObuffers
datainpreparationfortransmission.
TheMACtransmitterformatsframedatafromthetransmitFIFOandtransmitsthedatausingthe
CSMA/CDaccessprotocol.TheframeCRCcanbeautomaticallyappended,ifrequired.TheMAC
transmitteralsodetectstransmissionerrorsandpassesstatisticstothestatisticsregisters.
TheEthernetstatisticsarecountedandstoredinthestatisticslogicRAM.ThisstatisticsRAMkeepstrack
of36differentEthernetpacketstatistics.
StateRAMcontainstheheaddescriptorpointersandcompletionpointersregistersforbothtransmitand
receivechannels.
Theinterruptcontrollercontainstheinterruptrelatedregistersandlogic.The18rawEMACinterruptsare
inputtothissubmoduleandmaskedmoduleinterruptsareoutput.
TheEMACiscontrolledbyasetofmemory-mappedregisters.Thecontrollogicalsosignalstransmit,
receive,andstatusrelatedinterruptstotheCPUthroughtheEMACcontrolmodule.
TheclockandresetsubmodulegeneratesalltheEMACclocksandresets.Formoredetailsonreset
capabilities,seeSection2.14.1.
Afterreset,initialization,andconfiguration,thehostmayinitiatetransmitoperations.Transmitoperations
areinitiatedbyhostwritestotheappropriatetransmitchannelheaddescriptorpointercontainedinthe
stateRAMblock.ThetransmitDMAcontrollerthenfetchesthefirstpacketinthepacketchainfrom
memory.TheDMAcontrollerwritesthepacketintothetransmitFIFOinburstsof64-bytecells.Whenthe
thresholdnumberofcells,configurableusingtheTXCELLTHRESHbitintheFIFOcontrolregister
(FIFOCONTROL),havebeenwrittentothetransmitFIFO,oracompletepacket,whicheverissmaller,the
MACtransmittertheninitiatesthepackettransmission.TheSYNCblocktransmitsthepacketovertheMII
interfacesinaccordancewiththe802.3protocol.Transmitstatisticsarecountedbythestatisticsblock.
Receiveoperationsareinitiatedbyhostwritestotheappropriatereceivechannelheaddescriptorpointer
afterhostinitializationandconfiguration.TheSYNCsubmodulereceivespacketsandstripsoffthe
Ethernetrelatedprotocol.ThepacketdataisinputtotheMACreceiver,whichchecksforaddressmatch
andprocesseserrors.AcceptedpacketsarethenwrittentothereceiveFIFOinburstsof64-bytecells.
ThereceiveDMAcontrollerthenwritesthepacketdatatomemory.Receivestatisticsarecountedbythe
statisticsblock.
34EthernetMediaAccessController(EMAC)/SPRU941A–April2007
ManagementDataInput/Output(MDIO)
SubmitDocumentationFeedback