Texas Instruments TMS320DM643x DMP Switch User Manual


 
www.ti.com
2.9MediaIndependentInterface(MII)
2.9.1DataReception
2.9.1.1ReceiveControl
2.9.1.2ReceiveInter-FrameInterval
2.9.1.3ReceiveFlowControl
PeripheralArchitecture
TheEMACmoduleoperatesindependentlyoftheCPU.Itisconfiguredandcontrolledbyitsregisterset
mappedintodevicememory.Informationaboutdatapacketsiscommunicatedbyuseof16-byte
descriptorsthatareplacedinan8K-byteblockofRAMintheEMACcontrolmodule.
Fortransmitoperations,each16-bytedescriptordescribesapacketorpacketfragmentinthesystem's
internalorexternalmemory.Forreceiveoperations,each16-bytedescriptorrepresentsafreepacket
bufferorbufferfragment.Onbothtransmitandreceive,anEthernetpacketisallowedtospanoneor
morememoryfragments,representedbyone16-bytedescriptorperfragment.Intypicaloperation,thereis
onlyonedescriptorperreceivebuffer,buttransmitpacketsmaybefragmented,dependingonthe
softwarearchitecture.
AninterruptisissuedtotheCPUwheneveratransmitorreceiveoperationhascompleted.However,itis
notnecessaryfortheCPUtoservicetheinterruptwhilethereareadditionalresourcesavailable.Inother
words,theEMACcontinuestoreceiveEthernetpacketsuntilitsreceivedescriptorlisthasbeen
exhausted.Ontransmitoperations,thetransmitdescriptorsneedonlybeservicedtorecovertheir
associatedmemorybuffer.Thus,itispossibletodelayservicingoftheEMACinterruptifthereare
real-timetaskstoperform.
Eightchannelsaresuppliedforbothtransmitandreceiveoperations.Ontransmit,theeightchannels
representeightindependenttransmitqueues.TheEMACcanbeconfiguredtotreatthesechannelsasan
equalpriority"round-robin"queueorasasetofeightfixed-priorityqueues.Onreceive,theeightchannels
representeightindependentreceivequeueswithpacketclassification.Packetsareclassifiedbasedonthe
destinationMACaddress.EachoftheeightchannelsisassigneditsownMACaddress,enablingthe
EMACmoduletoactlikeeightvirtualMACadapters.Also,specifictypesofframescanbesenttospecific
channels.Forexample,multicast,broadcast,orother(promiscuous,error,etc.),caneachbereceivedon
aspecificreceivechannelqueue.
TheEMACkeepstrackof36differentstatistics,pluskeepsthestatusofeachindividualpacketinits
correspondingpacketdescriptor.
ThefollowingsectionsdiscusstheoperationoftheMediaIndependentInterface(MII)in10Mbpsand
100Mbpsmode.AnIEEE802.3compliantEthernetMACcontrolstheinterface.
DatareceivedfromthePHYisinterpretedandoutputtotheEMACreceiveFIFO.Interpretationinvolves
detectionandremovalofthepreambleandstart-of-framedelimiter,extractionoftheaddressandframe
length,datahandling,errorcheckingandreporting,cyclicredundancychecking(CRC),andstatistics
controlsignalgeneration.AddressdetectionandframefilteringisperformedoutsidetheMIIinterface.
The802.3standardrequiresaninterpacketgap(IPG),whichis24MIIclocks(96bittimes).However,the
EMACcantolerateareducedIPG(2MIIclocksor8bittimes)withacorrectpreambleandstartframe
delimiter.Thisintervalbetweenframesmustcomprise(inthefollowingorder):
1.AnInterpacketGap(IPG).
2.A7-bytepreamble(allbytes55h).
3.A1-bytestartofframedelimiter(5DH).
Whenenabledandtriggered,receiveflowcontrolisinitiatedtolimittheEMACfromfurtherframe
reception.Twoformsofreceivebufferflowcontrolareavailable:
Collision-basedflowcontrolforhalf-duplexmode
IEEE802.3xpauseframesflowcontrolforfull-duplexmode
SPRU941AApril2007EthernetMediaAccessController(EMAC)/35
ManagementDataInput/Output(MDIO)
SubmitDocumentationFeedback