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2.15.3MDIOModuleInitialization
PeripheralArchitecture
Example4.EMACControlModuleInitializationCode
Uint32tmpval;
/*
//GloballydisableEMAC/MDIOinterruptsinthecontrolmodule
*/
CSL_FINST(ECTL_REGS->EWCTL,ECTL_EWCTL_INTEN,DISABLE);
/*Waitabout100cycles*/
for(I=0;i<5;I++)
tmpval=ECTL_REGS->EWCTL;
/*SetInterruptTimerCount(PLL1clk/6)*/
ECTL_REGS->EWINTTCNT=1500;
/*
//InitializeMDIOandEMACModule
*/[Discussedlaterinthisdocument]
/*Enableglobalinterruptinthecontrolmodule*/
CSL_FINST(ECTL_REGS->EWCTL,ECTL_EWCTL_INTEN,ENABLE);
TheMDIOmoduleisusedtoinitiallyconfigureandmonitoroneormoreexternalPHYdevices.Other
thaninitializingthesoftwarestatemachine(detailsonthisstatemachinecanbefoundintheIEEE
802.3standard),allthatneedstobedonefortheMDIOmoduleistoenabletheMDIOengineandto
configuretheclockdivider.Tosettheclockdivider,supplyanMDIOclockof1MHZ.Forexample,
sincethebaseclockusedistheperipheralclock(PLL1/6),foraprocessoroperatingataPLL
frequencyof594MHZthedividercanbesetto99,withslowerMDIOclocksforslowerperipheralclock
frequenciesbeingperfectlyacceptable.
BoththestatemachineenableandtheMDIOclockdividerarecontrolledthroughtheMDIOcontrol
register(CONTROL).IfnoneofthepotentiallyconnectedPHYsrequiretheaccesspreamble,the
PREAMBLEbitinCONTROLcanalsobesettospeedupPHYregisteraccess.Thecodeforthismay
appearasinExample5.
Example5.MDIOModuleInitializationCode
#definePCLK99
...
/*EnableMDIOandsetupdivider*/
MDIO_REGS->CONTROL=CSL_FMKT(MDIO_CONTROL_ENABLE,YES)|
CSL_FMK(MDIO_CONTROL_CLKDIV,PCLK);
IftheMDIOmoduleistooperateonaninterruptbasis,theinterruptscanbeenabledatthistimeusing
theMDIOusercommandcompleteinterruptmasksetregister(USERINTMASKSET)forregisteraccess
andtheMDIOuserPHYselectregister(USERPHYSELn)ifatargetPHYisalreadyknown.
OncetheMDIOstatemachinehasbeeninitializedandenabled,itstartspollingall32PHYaddresses
ontheMDIObus,lookingforanactivePHY.Sinceitcantakeupto50µstoreadoneregister,itcan
besometimebeforetheMDIOmoduleprovidesanaccuraterepresentationofwhetheraPHYis
available.Also,aPHYcantakeupto3secondstonegotiatealink.Thus,itisadvisabletorunthe
MDIOsoftwareoffatime-basedeventratherthanpolling.
FormoreinformationonPHYcontrolregisters,seeyourPHYdevicedocumentation.
SPRU941A–April2007EthernetMediaAccessController(EMAC)/47
ManagementDataInput/Output(MDIO)
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