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5.14ReceiveInterruptMaskSetRegister(RXINTMASKSET)
EthernetMediaAccessController(EMAC)Registers
Thereceiveinterruptmasksetregister(RXINTMASKSET)isshowninFigure40anddescribedin
Table39.
Figure40.ReceiveInterruptMaskSetRegister(RXINTMASKSET)
3116
Reserved
R-0
158
Reserved
R-0
76543210
RX7MASKRX6MASKRX5MASKRX4MASKRX3MASKRX2MASKRX1MASKRX0MASK
R/WS-0R/WS-0R/WS-0R/WS-0R/WS-0R/WS-0R/WS-0R/WS-0
LEGEND:R=Readonly;R/W=Read/Write;WS=Write1toset,writeof0hasnoeffect;-n=valueafterreset
Table39.ReceiveInterruptMaskSetRegister(RXINTMASKSET)FieldDescriptions
BitFieldValueDescription
31-8Reserved0Reserved
7RX7MASK0-1Receivechannel7masksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
6RX6MASK0-1Receivechannel6masksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
5RX5MASK0-1Receivechannel5masksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
4RX4MASK0-1Receivechannel4masksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
3RX3MASK0-1Receivechannel3masksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
2RX2MASK0-1Receivechannel2masksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
1RX1MASK0-1Receivechannel1masksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
0RX0MASK0-1Receivechannel0masksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
82EthernetMediaAccessController(EMAC)/SPRU941A–April2007
ManagementDataInput/Output(MDIO)
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