Filter
Top Products
Setup Menus 91
Advanced Chipset Control Submenu
The advanced chipset control submenu provides several fields that allow
you to control various advanced features of the chipset. Table 17 lists the
fields and the options for each.
Table 17: Advanced Chipset Control Submenu
Field Options Description
Address Bit
Permuting
Disabled
Enabled
To be enabled, there must be a power of 2 number
of rows (2, 4, 8, or 16), all rows must be the same
size, and all populated rows must be adjacent and
start at row 0. Two-way or four-way permuting is
set automatically based on memory configuration.
Base RAM Step 1 MB
1 KB
Every location
Tests base memory once per MB, once per KB, or
at every location.
Extended RAM
Step
1 MB
1 KB
Every location
Tests extended memory once per MB, once per
KB, or at every location.
L2 Cache Enabled
Disabled
When enabled, the secondary cache is sized and
enabled. For Core Clock Frequency-to-System
Bus ratios equal to two, BIOS automatically
disables the L2 cache.
ISA Expansion
Aliasing
Enabled
Disabled
When enabled, every I/O access with an address in
the range x100-x3FFh, x500-x7FFh, x900-xBFF,
and xD00-xFFFh is internally aliased to the range
0100-03FFh before any other address range
checking is performed.
Memory Scrubbing Disabled
Enabled
When enabled, BIOS automatically detects and
corrects single bit errors (SBEs).
Restreaming Buffer Enabled
Disabled
When enabled, the data returned and buffered for
a Delayed Inbound Read can be reaccessed
following a disconnect.
Read Prefetch for
PXB0A
N/A Informational field only. Configures the number of
Dwords that are prefetched on Memory Read
Multiple commands.
Read Prefetch for
PXB0B
N/A Informational field only. Configures the number of
Dwords that are prefetched on Memory Read
Multiple commands.
3424.boo Page 91 Wednesday, September 2, 1998 9:23 AM