Intel SE8500HW4 Server User Manual


 
Processor and Chipset Intel® Server Board Set SE8500HW4
Revision 1.0
Intel order number D22893-001
8
2.2 Intel
®
E8500 Chipset
The Intel
®
E8500 Chipset is the highest performance, most scalable platform offering in the 64-
bit Intel
®
Xeon™ Processor MP family. The chipset represents the sixth-generation Intel four-
way multi-processor platform, is architected for multi-core processors and includes these
advanced features:
Support for up to four 64-bit Intel
®
Xeon™ Processors MP FSB operating at 667 MHz
Maintains coherency across both buses
Double-pumped 40-bit address buses with a total address bandwidth of 167 million
addresses/second
Quad-pumped, 64-bit data bus providing a bandwidth of 5.3 GB/s per bus
x8 Single Device Data Correction (x8 SDDC) technology for memory error correction
Hardware memory initialization
ECC protection on data signals and parity protection on address signals
Support for hot-plug memory and performance operations
This section provides an overview of the chipset components, for more detailed information
refer to the Intel
®
E8500 Chipset Datasheets referenced in the Appendix.
2.2.1 North Bridge (NB)
The Intel
®
E8500 Chipset North Bridge (NB) is the center of the system architecture and
provides interconnection to:
Up to four 64-bit Intel
®
Xeon™ Processors MP via two 667 MHz FSBs optimized for
server applications
Up to 64GB memory via four Independent Memory Interfaces (IMI)
I/O subsystem components via one PCI Express and the Intel
®
82801EB I/O Controller
Hub 5 (ICH5)
2.2.2 eXtended Memory Bridge (XMB)
The Intel
®
E8500 Chipset eXtended Memory Bridge (XMB) provides interface between the NB
and DDR2 400MHz DIMMs. The Intel
®
Server Board Set SE8500HW4 includes up to four
Memory Boards, each with an XMB and four DDR2 400MHz DIMM locations.