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DDR SDRAM Memory Interface Pins
Signal Name Type Description
MEMCLK_H/L[7]
O-IOD Differential DDR SDRAM clock to the top of DIMM 0 for
unbuffered DIMMs.1
MEMCLK_H/L[6] O-IOD Differential DDR SDRAM clock to the top of DIMM 1 for
unbuffered DIMMs.1
MEMCLK_H/L[5] O-IOD Differential DDR SDRAM clock to the bottom of DIMM 0 for
unbuffered DIMMs.1
MEMCLK_H/L[4] O-IOD Differential DDR SDRAM clock to the bottom of DIMM 1 for
unbuffered DIMMs.1
MEMCLK_H/L[3] O-IOD Differential DDR SDRAM clock to DIMM 3 for registered
DIMMs.1
MEMCLK_H/L[2] O-IOD Differential DDRS DRAM clock to DIMM 2 for registered
DIMMs.1
MEMCLK_H/L[1] O-IOD Differential DDR SDRAM clock to the middle of DIMM 1 for
unbuffered DIMMs, or DIMM 1 for registered DIMMs.1
MEMCLK_H/L[0] O-IOD Differential DDR SDRAM clock to the middle of DIMM 0 for
unbuffered DIMMs, or DIMM 0 for registered DIMMs.1
MEMCKEA
MEMCKEB
O-IOS Clock Enables to DIMMs. Used to gate clocks for power
management functionality.1
MEMDQS[17:0] B-IOS DRAM Data Strobes synchronous with MEMDATA and
MEMCHECK during DRAM read and writes.1
MEMDATA[63:0] B-IOS DRAM Interface Data Bus
MEMCHECK[7:0] B-IOS DRAM Interface ECC Check Bits
MEMCS_L[7:0] O-IOS DRAM Chip Selects 1
MEMRASA_L
MEMRASB_L
O-IOS DRAM Row Address Select. MEMRASA_L and
MEMRASB_L are functionally identical. Two copies are
provided to accommodate the loading of unbuffered DIMMs.1
MEMCASA_L
MEMCASB_L
O-IOS DRAM Column Address Select. MEMCASA_L and
MEMCASB_L are functionally identical. Two copies are
provided to accommodate the loading of unbuffered DIMMs.1
MEMWEA_L
MEMWEB_L
O-IOS DRAM Write Enable. MEMWEA_L and MEMWEB_L are
functionally identical. Two copies are provided to accommodate
the loading of unbuffered DIMMs.1
MEMADDA[13:0]
MEMADDB[13:0]
O-IOS DRAM Column/Row Address. Two copies are provided to
accommodate the loading of unbuffered DIMMs. During
precharges, activates, reads, and writes, the two copies are
inverted from each other (except A[10] which is used for
auto-precharge) to minimize switching noise. The signals are
inverted only when the bus is used to carry address
information.1
DDR SDRAM Memory Interface Pins (Continued)
Signal Name Type Description
MEMBANKA[1:0]
MEMBANKB[1:0]
O-IOS DRAM Bank Address. Two copies are provided to
accommodate the loading of unbuffered DIMMs. During
precharges, activates, reads, and writes the two copies are
inverted from each other to minimize switching noise. The
signals are inverted only when the bus is used to carry address
information.1
MEMRESET_L O-IOS DRAM Reset pin for Suspend-to-RAM power management
mode. This pin is required for registered DIMMs only.
MEMVREF VREF DRAM Interface Voltage Reference 1
MEMZP A Compensation Resistor tied to VSS 1
MEMZN A Compensation Resistor tied to 2.5 V 1
Note: For connection details and proper resistor values, see the AMD Athlon™ 64 Processor
Motherboard Design Guide, order# 24665.
HyperTransport™ Technology Pin Descriptions
Note: 1.These pins are used in an alternating fashion to compensate R TT by internal comparison to 3/4
VLDT and 1/4 VLDTand compensate R ON by comparison to each other around 1/2 VLDT.
For proper resistor value, see theAMD Athlon™ 64 Processor Motherboard Design Guide, order#
24665.
2.The unused L0_CTLIN_H/L[1] pins must be properly terminated such that the true pin is pulled
High and thecomplement is pulled Low. Refer to the AMD Athlon™ 64 Processor Motherboard
Design Guide, order# 24665, for details.
Signal Name Type Description
L0_CLKIN_H/L[1:0] I-HT Link 0 Clock Input
L0_CTLIN_H/L[1:0] I-HT Link 0 Control Input 2
L0_CADIN_H/L[15:0] I-HT Link 0 Command/Address/Data Input
L0_CLKOUT_H/L[1:0] O-HT Link 0 Clock Outputs
L0_CTLOUT_H/L[1:0] O-HT Link 0 Control Output
L0_CADOUT_H/L[15:0] O-HT Link 0 Command/Address/Data Outputs
L0_REF1 A Compensation Resistor to VLDT 1
L0_REF0 A Compensation Resistor to VSS 1
5.1 AMD Mobile Athlon 64(ClawHammer) Processor(1)
5. Pin Descriptions of Major Components
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