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74
AGP Bus Interface (Continued)
Signal Name Pin # I/O Signal Description
AGP8XDT#
Y2 I AGP 8x Transfer Mode Detect. Low indicates that the external
graphics card can support 8x transfer mode
GRBF(GRBF#
for 4x)
AD6 I Read Buffer Full. Indicates if the master (graphics controller)
is ready to accept previously requested low priority read data.
When GRBF# is asserted, the North Bridge will not return low
priority read data to the graphics controller.
GWBF(GWBF#
for 4x)
AC1 I
Write Buffer Full.
GSBA[7:0]#
(GSBA[7:0] for
4x)
(see pin
list)
I Side Band Address. Provides an additional bus to pass address
and command information from the master (graphics controller)
to the target (North Bridge). These pins are ignored until
enabled.
GSBSTBF
(GSB
STB for 4x),
GSBSTBS
(GSBS
TB# for 4x)
AF1
AE1
I
Side Band Strobe.
Driven by the master to provide timing for
GSBA[7:0]. 8x mode uses GSBSTBF (iBFirstlr strobe) and
GSBSTBS (iBSecondl) strobe). These signals are interpreted as
GSBSTB & GSBSTB# for AGP4x.
GST[2:0]
AB1
AA1
AA2
O Status (AGP only). Provides information from the arbiter to a
master to indicate what it may do. Only valid while GGNT# is
asserted.
000 Indicates that previously requested low priority read or
flush data is being returned to the master (graphics
controller).
001 Indicates that previously requested high priority read data is
being returned to the master.
010 Indicates that the master is to provide low priority write
data for a previously enqueued write command.
011 Indicates that the master is to provide high priority write
data for a previously enqueued write command.
100 Reserved. (arbiter must not issue, may be defined in the
future).
101 Reserved. (arbiter must not issue, may be defined in the
future).
110 Reserved. (arbiter must not issue, may be defined in the
future).
111 Indicates that the master (graphics controller) has been
given permission to start a
b
us transaction. The master may
enqueue AGP requests by asserting PIPE# or start a PCI
transaction by asserting GFRM#. ST[2:0] are always
outputs from the target (North Bridge logic) and inputs to
the master (graphics controller).
AGP Bus Interface (Continued)
Signal Name Pin # I/O Signal Description
GSTOP(GSTOP
# for 4x)
AC12 IO Stop (PCI transactions only). Asserted by the target to request
the master to stop the current transaction. Interpreted as active
high for AGP 8x.
GREQ(GREQ#
for 4x)
Y1 I Request. Master (graphics controller) request for use of the
AGP bus.
GGNT(GGNT#
for 4x)
AA3 O Grant. Permission is given to the master (graphics controller) to
use the AGP bus.
GSERR(GSERR
# for 4x)
AC15 IO
AGP System Error.
Note: The AGP interface pins can be optionally configured as additional interfaces for connecting to
external display devices. For simplification of the AGP pin description tables above and on the next
page, that multiplexing is not shown here (see isAdditional 12C InterfaceslÓo, and display pin
description tables later in this document for more information).
Note: The AGP interface pins can be optionally configured as additional interfaces for connecting to
external display devices. For simplification of the AGP pin description tables above and on the next
page, that multiplexing is not shown here (see isAdditional I2C Interfacesll and display pin description
tables later in this document for more information).
Note: Separate system interrupts are not provided for AGP. The AGP connector provides interrupts via
PCI bus INTA-B#.
Note: A separate reset is not required for the AGP bus (RESET# resets both PCI and AGP buses)
Note: Two mechanisms are provided by the AGP bus to enqueue master requests: GPIPE# (to send
addresses multiplexed on the AD lines) and the SBA port (to send addresses unmultiplexed). AGP
masters implement one or the other or select one at initialization time (they are not allowed to change
during runtime). Only one of the two will be used; the signals associated with the other will not be used.
GRBF# has an internal pullup to maintain it in the de-asserted state in case it is not implemented on the
master device. AGP 8x mode allows only SBA (GPIPE# isn™t used in 8x mode).
Note: AGP 8x signal levels are 0V and 0.8V. AGP 8x mode maintains most signals at a low level when
inactive resulting in no current flow.
5.2 VIA K8N800 North Bridge(2)
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