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8399
N/B Maintenance
N/B Maintenance
89
Power and Ground
Signal Name Pin # I/O Signal Description
VSUS33 AA4,
AB4-6
P
Suspend Power. 3.3V ±5%. Always available unless the
mechanical switch of the power supply is turned off. If the
ihsoft-offlÉD state is not implemented, then this pin can be
connected to VCC33. Signals powered by or referenced to
this plane are: PWRGD, RSMRST#, PWRBTN#,
SMBCK1/2, SMBDT1/2, GPO0, SUSA# / GPO1, SUSB# /
GPO2, SUSC#, SUSST1# / GPO3, SUSCLK / GPO4,
GPI1, GPI2 / EXTSMI#, GPI3 / RING#, GPI4 / LID, GPI5
/ BATLOW#, GPI6 / PME#, SMBALRT#
VSUS25 T4, U4 P
Suspend Power. 2.5V ±5%.
VSUSUSB C24 P
USB Suspend Power. 2.5V ±5%.
VBAT AF4 P
RTC Battery. Battery input for internal RTC (RTCX1,
RTCX2)
VLVREF H22 P
V-Link Voltage Reference. 0.9V ±5% for 4x transfers and
0.625V ±5% for 8x transfers.
VLCOMP J22 AI V-Link Compensation.
VCCVK (see pin
list)
P
V-Link Compensation Circuit Voltage. 2.5V ±5%
MIIVCC D9,
E9-11
P
LAN MII Power. 3.3V ±5%.Power for LAN Media
Independent Interface (interface to external PHY). Connect
to VCC33 through a ferrite bead.
MIIVCC25 D12.
E12
P
LAN MII Suspend Power. 2.5V ±5%.
LANVCC E7 P
LAN Power. 2.5V ±5%. Power for LAN. Connect to VCC
through a ferrite bead.
LANGND E6 P
LAN Ground. Connect to GND through a ferrite bead.
USBVCC (see pin
list)
P
USB 2.0 Differential Output Power. 3.3V ±5%. Power
for USB differential outputs (USBP0+, P0Œ, P1+, P1Œ,
P2+, P2Œ, P3+, P3Œ, P4+, P4Œ, P5+, P5Œ). Connect to
VSUS33 through a ferrite bead.
USBGND (see pin
list)
P
USB 2.0 Differential Output Ground. Connect to GND
through a ferrite bead.
VCCUPLL A23,
B23
P
USB 2.0 PLL Analog Voltage. 2.5V ±5%. Connect to
VCC through a ferrite bead.
GNDUPLL C23,
D23
P
USB 2.0 PLL Analog Ground. Connect to GND through a
ferrite bead.
PLLVCC T22 P
PLL Analog Power. 2.5V ±5%. Connect to VCC through
a ferrite bead.
PLLGND U22 P
PLL Analog Ground. Connect to GND through a ferrite
bead.
Strap Pins for North Bridge Configuration
Signal Name Pin # Function Description Note
SDCS3#
AF26
NB
Configuratio
n
SDCS3# signal state is reflected on
signal pinVD[7] during power up
for North Bridgeconfiguration.
Check the
NorthBridge DS
fordetails
SDA2
AE24
NB
Configuratio
n
SDA2 signal state is reflected on
signal pinVD[6] during power up
for North Bridgeconfiguration.
Check the
NorthBridge DS
fordetails
SDA1
AC22
NB
Configuratio
n
SDA1 signal state is reflected on
signal pinVD[5] during power up
for North Bridgeconfiguration.
Check the
NorthBridge DS
fordetails
SDA0
AF24
NB
Configuratio
n
SDA0 signal states is reflected on
signal pinsVD[4] during power up
for North Bridgeconfiguration.
Check the
NorthBridge DS
fordetails
Strap_VD3
AC6
NB
Configuratio
n
Strap_VD3 signal state is reflected
on signal pinVD[3] during power
up for North Bridgeconfiguration.
Check the
NorthBridge DS
fordetails
Strap_VD2
AD5
NB
Configuratio
n
Strap_VD2 signal state is reflected
on signal pinVD[2] during power
up for North Bridgeconfiguration.
Check the
NorthBridge DS
fordetails
Strap_VD1
AE5
NB
Configuratio
n
Strap_VD1 signal state is reflected
on signal pin, VD[1] during power
up for North Bridge configuration.
Check the North
Bridge DS for details
Strap_VD0
AF5
NB
Configuratio
n
Strap_VD0 signal state is reflected
on signalpin, VD[0] during power
up for North Bridgeconfiguration.
Check the
NorthBridge DS
fordetails
Note: Internal Pullups are present on pins KBCK, KBDT, MSCK, MSDT, SERIRQ, LAD[3:0]
Internal Pulldowns are present on all LAN pins
Power and Ground
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Signal Name Pin # I/O Signal Description
VCC33 (see pin
list)
P
I/O Power. 3.3V ±5%
VCC (see pin
list)
P Core Power. 2.5V ±5%. This supply is turned on
only when the mechanical switch on
the power
supply is turned on and the PWRON signal is
conditioned high.
GND (see pin
list)
P
Ground. Connect to primary motherboard ground plane.
5.3 VIA VT8235CD South Bridge(10)
MiTac Secret
Confidential Document