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73
AGP Bus Interface
Signal Name Pin # I/O Signal Description
GD[31:0]
(see pin
list)
IO Address / Data Bus. Address is driven with GDS assertion for
AGP-style transfers and with GFARME# assertion for PCI-style
transfers.
GC#BE[3:0]
(GCBE[3:0]# for
4x mode)
AC7
AD11
AF11
AD15
IO Command / Byte Enable. (Interpreted as GC/BE# for AGP
2x/4x and GC#/BE for 8x). For AGP cycles these pins provide
command information (different commands than for PCI) driven
by the master (graphics controller) when requests are being
enqueued using GPIPE# (2x/4x only as GPIPE# isn™t used in
8x mode). These pins provide valid byte information during
AGP write transactions and are driven by the master. The target
(this chip) drives these lines to io0000lt during the return of
AGP read data. For PCI cycles, commands are driven with
GFARME# assertion. Byte enables corresponding to supplied or
requested data are driven on following clocks.
GPAR
AC16 IO AGP Parity. A single parity bit is provided over GD[31:0] and
GC#BE[3:0].
GDBIH /
GPIPE#GDBIL
AC5
AC4
IO Dynamic Bus Inversion High / Low. AGP 8x transfer mode
only. Driven by the source to indicate whether the
corresponding data bit group (GDBIH for GD[31:16] and
GDBIL for GD[15:0]) needs to be inverted on the receiving end
(1 on GDBIx indicates that the corresponding data bit group
should be inverted). Used to limit the number of simultaneously
switching outputs to 8 for each 16-pin group.
Pipelined Request. Not used by AGP 8x. Asserted by the
master (external graphics controller) to indicate that a full-width
request is to be enqueued by the target (North Bridge). The
master enqueues one request each rising edge of GCLK while
GPIPE# is asserted. When GPIPE# is deasserted no new
requests are enqueued across the AD bus.
Note: See RxAE[1] for GPIPE# / GDBIH pin function
selection.
GADSTB0F(GA
DSTB0 for 4x),
GADSTB0S(GA
DSTB0# for 4x)
AE15
AF15
IO Bus Strobe 0. Source synchronous strobes for GD[15:0] (the
agent that is providing the data drives these signals). GDS0
provides timing for 2x data transfer mode; GDS0 and GDS0#
provide timing for 4x mode. For 8x transfer mode, GDS0 is
interpreted as GDS0F (i1Firstl. strobe) and GDS0# as GDS0S
(iSSecondl. strobe).
AGP Bus Interface (Continued)
Signal Name Pin # I/O Signal Description
GADSTB1F(GA
DSTB1 for 4x),
GADSTB1S(GA
DSTB1# for 4x)
AE7
AF7
IO Bus Strobe 1. Source synchronous strobes for GD[31:16] (i.e.,
the agent that is providing the data drives these signals). GDS1
provides timing for 2x data transfer mode; GDS1 and GDS1#
provide timing for 4x transfer mode. For 8x transfer mode,
GDS1 is interpreted as GDS1F (iSFirstle strobe) and GDS1# as
GDS1S (iSSecondld strobe).
GFRAME(GFR
AME# for 4x)
AC9 IO Frame. Assertion indicates the address phase of a PCI transfer.
Negation indicates that one more data transfer is desired by the
cycle initiator. Interpreted as active high for 8x.
GIRDY(GIRDY
# for 4x)
AC10 IO Initiator Ready. (Interpreted as active low for PCI/AGP2x/4x
and high for AGP 8x). For AGP write cycles, the assertion of
this pin indicates that the master is ready to provide all
write data for the current transaction. Once this pin is asserted,
the master is not allowed to insert wait states. For AGP read
cycles, the assertion of this pin indicates that the master is ready
to transfer a subsequent block of read data. The master is never
allowed to insert a wait state during the initial block of a read
transaction. However, it may insert wait states after each block
transfers. For PCI cycles, asserted when the initiator is ready
for data transfer.
GTRDY(GTRD
Y# for 4x)
AC14 IO Target Ready. (Interpreted as active low for PCI/AGP2x/4x
and high for AGP 8x). For AGP cycles, indicates that the target
is ready to provide read data for the entire transaction (when
the transaction can complete within four clocks) or is ready to
transfer a (initial or subsequent) block of data when the transfer
requires more than four clocks to complete. The target is
allowed to insert wait states after each block transfer for both
read and write transactions. For PCI cycles, asserted when the
target is ready for data transfer.
GDEVSEL(GDE
VSEL# for 4x
mode)
AC11 IO Device Select (PCI transactions only). This signal is driven by
the North Bridge when a PCI initiator is attempting to access
main memory. It is an input when the chip is acting as PCI
initiator. Not used for AGP cycles. Interpreted as active high for
AGP 8x.
5.2 VIA K8N800 North Bridge(1)
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