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AGP-Multiplexed Digital Video Port 1 (GDVP1) – TV Encoder
Signal Name AGP Name Pin # I/O Signal Description
GTVD11 / GDVP1D11,
GTVD10 / GDVP1D10,
GTVD9 / GDVP1D9,
GTVD8 / GDVP1D8,
GTVD7 / GDVP1D7,
GTVD6
/ GDVP1D6,
GTVD5 / GDVP1D5,
GTVD4 / GDVP1D4,
GTVD3 / GDVP1D3,
GTVD2 / GDVP1D2,
GTVD1 / GDVP1D1,
GTVD0 / GDVP1D0
GC#BE3
GD26
GD24
GD30
GD28
GD29
GSBA4#
GD27
GSBA5#
GSBSTBS
GSBSTBF
GSBA2#
AC7
AE6
AF6
AE4
AF5
AF4
AF2
AD5
AD3
AE1
AF1
AD1
O
Data.
GTVHS / GDVP1HS GSBA3# AD2 O Horizontal Sync. Internally pulled down.
GTVVS / GDVP1VS GSBA0# AC2 O Vertical Sync. Internally pulled down.
GTVDE / GDVP1DE GSBA1# AC3 O Display Enable. Internally pulled down.
GTVCLKR /
GDVP1DET
GD31 AD4 I Clock In. Input from TV encoder. Internally
pulled down.
GTVCLK /
GDVP1CLK
GSBA6# AE3 O Clock Out. Output to TV encoder. Internally
pulled down.
GTVCLK# /
GDVP1CLK#
GSBA7# AF3 O Clock Out Complement. Output to TV
encoder. Internally pulled down.
The above pins may be connected to an external TV Encoder chip such as a VIA VT1623 or
VT1623M for driving a TV set.
I/O pads for the pins on this page are powered by VCC15AGP (1.5V I/O).
24-Bit / Dual 12-Bit Flat Panel Display Interface
Signal Name AGP Name Pin # I/O Signal Description
FPD23 / FPD0D11,
FPD22 / FPD0D10,
FPD21 / FPD0D09,
FPD20 / FPD0D08,
FPD19 / FPD0D07,
FPD18 / FPD0D06,
FPD17 / FPD0D05,
FPD16 / FPD0D04,
FPD15 / FPD0D03,
FPD14 / FPD0D02,
FPD13 / FPD0D01,
FPD12 / FPD0D00,
FPD11 / FPD1D11,
FPD10 / FPD1D10,
FPD09 / FPD1D09,
FPD08 / FPD1D08,
FPD07 / FPD1D07,
FPD06 / FPD1D06,
FPD05 / FPD1D05,
FPD04 / FPD1D04,
FPD03 / FPD1D03,
FPD02 / FPD1D02,
FPD01 / FPD1D01,
FPD00 / FPD1D00
GD11
GD13
GD14
GD15
GC#BE2
GD16
GD17
GD18
GD23
GD20
GD22
GADSSTB1
F
GD1
GD0
GD3
GD4
GD5
GD6
GD7
GADSTB0F
GC#BE0
GADSTB0S
GD10
GD12
AE13
AD12
AF12
AE12
AD11
AD10
AE10
AF10
AD8
AF9
AE9
AE7
AD18
AF18
AF17
AD17
AD16
AE16
AF16
AE15
AD15
AF15
AD13
AF13
O Flat Panel Data. For 24-bit or dual 12-bit flat
panel display modes.
Two FPD interface modes, 24-bit and dual
12-bit, are supported.
Strapping pin DVP0D4 is used to select the
interface mode to the LVDS transmitter chip:
Strap High (3C5.12[4]=1): 24-bit
Strap Low (3C5.12[4]=0): Dual 12-bit
In in24-bitl] mode, only one set of control pins
is required. However, in dual 12-bit mode, the
K8N800 Version CD provides two sets of
control signals that are required for certain
LVDS transmitter chips.
In 24-bit mode, two operating modes are
supported:
3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=0
Double data rate: each rising & falling clock
edge transmits a complete 24-bit pixel
3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=1
Single data rate: each clock rising edge
transmits a complete 24-bit pixel
In dual 12-bit mode,
3C5.12[4]=0 & 3x5.88[2] = 1
Each rising and falling clock edge transmits half
(12 bits) of two 24-bit pixels
FPHS
GFRAME AC9 O Flat Panel Horizontal Sync. 24-bit mode or
port 0 of dual 12-bit mode.
FPVS
GDEVSEL AC11 O Flat Panel Vertical Sync. 24-
b
it mode or port 0
of dual 12-bit mode.
FPDE
GD19 AD9 O Flat Panel Data Enable. 24-bit mode or port 0
of dual 12-bit mode
FPDET
GADSTB1S AF7 I Flat Panel Detect. 24-
b
it mode or port 0 of dual
12-bit mode
FPCLK
GD21 AF8 O Flat Panel Clock. 24-bit mode or port 0 of dual
12-bit mode
FPCLK# GWBF AC1 O Flat Panel Clock Complement. 24-bit mode or
port 0 of dual 12-bit
Mode.
Flat Panel Power Control (Muxed with AGP)
Signal Name AGP Name Pin # I/O Signal Description
ENAVDD
GST1 AA1 IO
Enable Panel VDD Power.
ENAVEE
GST0 AA2 IO
Enable Panel VEE Power.
ENABLT
GST2 AB1 IO
Enable Panel Back Light.
Note: I/O pads for all pins on this page are powered by VCC15AGP (i.e., 1.5V I/O).
5.2 VIA K8N800 North Bridge(5)
MiTac Secret
Confidential Document