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UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface
Signal Name Pin # I/O Signal Description
PDRDY
/PDDMARDY
/PDSTROBE
Y22 I EIDE Mode: Primary I/O Channel Ready. Device ready
indicator UltraDMA Mode: Primary Device DMA Ready.
Output flow control. The device mayassert DDMARDY to pause
output transfers Primary Device Strobe. Input data strobe (both
edges). The device may stop DSTROBE to pause input data
transfers
SDRDY
/SDDMARDY
/SDSTROBE
AF17 I EIDE Mode: Secondary I/O Channel Ready. Device ready
indicator UltraDMA Mode: Secondary Device DMA Ready.
Output flow control. The devicemay assert DDMARDY to pause
output transfers Secondary Device Strobe. Input data strobe (both
edges). The device may stop DSTROBE to pause input data
transfers
PDIOR#
/PHDMARDY
/PHSTROBE
W26 O EIDE Mode: Primary Device I/O Read. Device read strobe
UltraDMA Mode: Primary Host DMA Ready. Primary channel
input flow control. Thehost may assert HDMARDY to pause input
transfers Primary Host Strobe. Output data strobe (both edges).
The host may stop HSTROBE to pause output data transfers
SDIOR#
/SHDMARDY
/SHSTROBE
AF23 O EIDE Mode: Secondary Device I/O Read. Device read strobe
UltraDMA Mode: Secondary Host DMA Ready. Input flow
control. The host mayassert HDMARDY to pause input transfers
Host Strobe B. Output strobe (both edges). The host may stop
HSTROBE to pause output data transfers
PDIOW#
/PSTOP
Y25 O EIDE Mode:
Primary Device I/O Write.
Device write strobe
UltraDMA Mode:
Primary Sto
p. Stop transfer: Asserted by the
host prior to initiation of
an UltraDMA burst; negated by the host before data is transferred in
an UltraDMA burst. Assertion of STOP by the host during or after
data transfer in UltraDMA mode signals the termination of the
burst.
SDIOW#
/SSTOP
AE23 O EIDE Mode: Secondary Device I/O Write. Device write strobe
UltraDMA Mode: Secondary Stop. Stop transfer: Asserted by the
host prior to initiation of an UltraDMA burst; negated by the host
before data is transferred in an UltraDMA burst. Assertion of STOP
by the host during or after data transfer in UltraDMA mode signals
the termination of the burst.
PDDRQ
Y23 I Primary Device DMA Request. Primary channel DMA request
SDDRQ
AD17 I Secondary Device DMA Request. Secondary channel DMA
request
UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface (Continued)
Signal Name Pin # I/O Signal Description
PDDACK#
Y24 O Primary Device DMA Acknowledge. Primary channel DMA
acknowledge
SDDACK#
AD23 O Secondary Device DMA Acknowledge. Secondary channel DMA
acknowledge
IRQ14
AD24 I
Primary Channel Interrupt Request.
IRQ15
AE26 I
Secondary Channel Interrupt Request.
PDCS1#
V22 O Primary Master Chip Select. This signal corresponds to CS1FX#
on the primary IDE connector.
PDCS3#
V23 O Primary Slave Chip Select. This signal corresponds to CS3FX# on
the primary IDE connector.
SDCS1# / strap AF25 O Secondary Master Chip Select. This signal corresponds to
CS17X# on the secondary IDE connector. Strap low (resistor to
ground) to enable serial EEPROM interface via the MII bus (this
disables the EExx pins). This pin has an internal pullup to default to
serial EEPROM interface via the EExx pins.
SDCS3# / strap AF26 O Secondary Slave Chip Select. This signal corresponds to CS37X#
on the secondary IDE connector. Strap information is
communicated to the north bridge via VD[7].
PDA[2-0]
W24,
V25,
W23
O Primary Disk Address. PDA[2:0] are used to indicate which byte
in either the ATA command block or control block is being
accessed.
SDA[2-0] / strap AE24,
AC22,
AF24
O Secondary Disk Address. SDA[2:0] are used to indicate which
byte in either the ATA command block or control block is being
accessed. Strap information is communicated to the north bridge via
VD[6:4].
PDD[15-0]
(see pin
list)
IO
Primary Disk Data.
SDD[15-0]
(see pin
list)
IO
Secondary Disk Data.
Serial IRQ
Signal Name Pin # I/O Signal Description
SERIRQ
AD9 I Serial IRQ. This pin has an internal pull-up resistor.
5.3 VIA VT8235CD South Bridge(5)
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