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V-Link Interface
Signal Name Pin # I/O Signal Description
VD[7:0]
(see pin
list)
IO Data Bus. These pins are also used to send strap information to
the chipset north
bridge. At power up, VD7 reflects the state of a strap on
SDCS3#, VD[6:4] reflect
the state of straps on pins SDA[2:0], and VD[3:0] reflect the
state of straps on pins
Strap_VD3-0. The specific interpretation of these straps is north
bridge chip design
dependent.
VPAR F24 IO Parity. If the VPAR function is implemented in a compatible
manner on the north
bridge, this pin should be connected to the north bridge VPAR
pin (P4X333,
P4X400, P4X800, KT400). If VPAR is not implemented in the
north bridge chip or
is incompatible with the 8235CE (4x V-Link north bridges)
connect this pin to an
8.2K pullup to 2.5V (Pro266, Pro266T, KT266, KT266A,
KT333, P4X266, PN266,
KN266, KM266, P4M266, P4N266). See app note AN222 for
details.
VBE#
G24 IO
Byte Enable.
VCLK
L22 I
V-Link Clock.
UPCMD
K23 O
Command from Client-to-Host.
DNCMD
K25 I
Command from Host-to-Client.
UPSTB
J26 O
Strobe from Client-to-Host.
UPSTB#
J24 O
Complement Strobe from Client-to-Host.
DNSTB
K26 I
Strobe from Host-to-Client.
DNSTB#
H24 I
Complement Strobe from Host-to-Client.
CPU Interface
Signal Name Pin # I/O Signal Description
A20M#
U26 OD A20 Mask. Connect to A20 mask input of the CPU to control
address bit-20 generation.
Logical combination of the A20GATE input (from internal or
external keyboard controller)
and Port 92 bit-1 (Fast_A20).
FERR# U24 I Numerical Coprocessor Error. This signal is tied to the
coprocessor error signal on the
CPU. Internally generates interrupt 13 if active. Output voltage
swing is programmable tot
1.5V or 2.5V by Device 17 Function 0 Rx67[2].
IGNNE#
T24 OD Ignore Numeric Error. This pin is connected to the CPU
iPignore errorlr pin.
INIT#
R26 OD
Initialization.
The VT8235 Version CE asserts INIT# if it
detects a shut-down special
cycle on the PCI bus or if a soft reset is initiated by the register
INTR
T25 OD CPU Interrupt. INTR is driven by the VT8235 Version CE to
signal the CPU that an
interrupt request is pending and needs service.
NMI
T26 OD Non-Maskable Interrupt. NMI is used to force a
non-maskable interrupt to the CPU. The
VT8235 Version CE generates an NMI when PCI bus SERR# is
asserted.
SLP#
V26 OD Sleep. Used to put the CPU to sleep.
SMI#
U25 OD System Management Interrupt. SMI# is asserted by the
VT8235 Version CE to the CPU
in response to different Power-Management events.
STPCLK#
R24 OD Stop Clock. STPCLK# is asserted by the VT8235 Version CE
to the CPU to throttle the
processor clock.
Note: Connect each of the above signals to 150 §Ù pullup resistors to VCC_CMOS (see Design Guide).
5.3 VIA VT8235CD South Bridge(1)
MiTac Secret
Confidential Document