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National Instruments Corporation I-3 DIO 6533 User Manual
H
handshake timing, 5-4 to 5-33
8255 emulation, 5-4 to 5-7
burst mode, 5-27 to 5-33
leading-edge mode, 5-14 to 5-18
level-ACK mode, 5-9 to 5-14
long-pulse mode, 5-19 to 5-22
trailing-edge mode, 5-23 to 5-27
handshaking protocols, 3-8 to 3-10
8255 emulation, 3-9
burst mode, 3-10
comparison of protocols, 3-10 to 3-11
leading-edge pulse, 3-9
level ACK, 3-9
long pulse, 3-9
trailing-edge pulse, 3-9
handshaking transfer
controlling line polarities, 3-13
controlling startup sequence, 3-12
overview, 3-6
starting, 3-12 to 3-13
hardware configuration. See configuration.
hardware groups, 3-5
hardware installation. See installation.
hardware overview, 3-1 to 3-14
block diagrams
AT-DIO-32HS, 3-3
DAQCard-6533, 3-4
PCI-DIO-32HS/PXI-6533, 3-2
strobed I/O, 3-5 to 3-13
comparison of handshaking
protocols, 3-10 to 3-11
definition, 3-5
handshaking protocols, 3-8 to 3-10
pattern and change detection, 3-6 to
3-8
starting handshaking transfer, 3-12 to
3-13
transfer rates, 3-13 to 3-14
achieving highest possible rates, 3-13
to 3-14
maximum, 3-13
I
I/O connector, 4-1 to 4-9
control signal summary, 4-7
exceeding maximum ratings (note), 4-1
pin assignments (table), 4-2
RTSI bus interface, 4-7 to 4-9
signal characteristics, 4-6
signal descriptions (table), 4-3 to 4-5
initial state of signals, 4-6
installation
AT-DIO-32HS, 2-3
DAQCard-6533, 2-3 to 2-4
PCI-DIO-32HS, 2-1 to 2-2
PXI-6533, 2-2 to 2-3
software, 2-1
unpacking the DIO 6533, 1-8
interrupt channel selection, 2-6 to 2-9
PC AT 16-bit DMA channel assignment
map (table), 2-9
PC AT I/O address map (table), 2-6 to 2-8
PC AT interrupt assignment map (table),
2-8 to 2-9
L
leading-edge mode, 5-14 to 5-18
input, 5-14, 5-15
output, 5-14, 5-16
purpose and use, 3-9
timing specifications
input timing (figure), 5-17
output timing (figure), 5-18
level ACK mode, 5-9 to 5-13
input, 5-9, 5-10
output, 5-10 to 5-11