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Chapter 5 Signal Timing
DIO 6533 User Manual 5-16 © National Instruments Corporation
Figure5-13 shows an output transfer in leading-edge mode.
Figure 5-13. Leading-Edge Mode Output
Leading-Edge Mode Timing Specifications
Figures5-14 and5-15 show the timing diagrams for leading-edge
mode.
Wait
For
Data
Wait
For
REQ
Programmable
Delay
Programmable
Delay
Wait
For
REQ
When REQ
Asserted
When 6533 Device
Has Data to Output,
Output Data*
Clear
ACK
Pulse
When REQ
Unasserted
Initial State
ACK Cleared
Send
ACK
Pulse
* With REQ-edge latching enabled, the data written is
delayed until the next inactive-going REQ edge.