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National Instruments Corporation ix DIO 6533 User Manual
Figure 5-11. Level-ACK Mode Output Timing .........................................................5-13
Figure 5-12. Leading-Edge Mode Input.....................................................................5-15
Figure 5-13. Leading-Edge Mode Output ..................................................................5-16
Figure 5-14. Leading-Edge Mode Input Timing ........................................................5-17
Figure 5-15. Leading-Edge Mode Output Timing......................................................5-18
Figure 5-16. Long-Pulse Mode Input .........................................................................5-19
Figure 5-17. Long-Pulse Mode Output.......................................................................5-20
Figure 5-18. Long-Pulse Mode Input Timing ............................................................5-21
Figure 5-19. Long-Pulse Mode Output Timing..........................................................5-22
Figure 5-20. Trailing-Edge Mode Input .....................................................................5-24
Figure 5-21. Trailing-Edge Mode Output...................................................................5-25
Figure 5-22. Trailing-Edge Mode Input Timing ........................................................5-26
Figure 5-23. Trailing-Edge Mode Output Timing......................................................5-27
Figure 5-24. Input Burst Mode Transfer Example .....................................................5-28
Figure 5-25. Output Burst Mode Transfer Example...................................................5-29
Figure 5-26. Burst Mode Output Timing (Default)....................................................5-30
Figure 5-27. Burst Mode Input Timing (Default).......................................................5-31
Figure 5-28. Burst Mode Output Timing (PCLK Reversed)......................................5-32
Figure 5-29. Burst Mode Input Timing (PCLK Reversed) ........................................5-33
Figure B-1. 68-to-50-Pin Adapter Pin Assignments .................................................B-2
Table
Table 1-1. Pins Used by the PXI-6533 Device .......................................................1-3
Table 2-1. PC AT I/O Address Map .......................................................................2-6
Table 2-2. PC AT Interrupt Assignment Map.........................................................2-8
Table 2-3. PC AT 16-Bit DMA Channel Assignment Map....................................2-9
Table 3-1. 6533 Handshaking Protocols .................................................................3-11
Table 4-1. Signal Descriptions................................................................................4-3
Table 4-2. Control Signal Summary .......................................................................4-7