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Chapter 5 Signal Timing
© National Instruments Corporation 5-11 DIO 6533 User Manual
Figure5-9 shows an output transfer in level-ACK mode.
Figure 5-9. Level-ACK Mode Output
Level-ACK Mode Timing Specifications
Figures5-10 and5-11 show the timing diagrams for level-ACK mode.
Wait
For
Data
Wait
For
REQ
Programmable
Delay
Programmable
Delay
Wait
For
REQ
When REQ
Asserted
Clear ACK
When 6533 Device
Has Data to Output,
Output Data*
When REQ
Unasserted
Initial State
ACK Cleared
Send
ACK
* With REQ-edge latching enabled, the data written is
delayed until the next inactive-going REQ edge.