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Chapter 3 Hardware Overview
DIO 6533 User Manual 3-10 © National Instruments Corporation
Burst Mode
The 6533 device sends or receives a clock signal to or from the
peripheral device over the PCLK line. Every cycle, the 6533 device
asserts an ACK signal if ready for a transfer, and the peripheral device,
likewise, asserts a REQ signal if ready for a transfer. Each cycle during
which both the 6533 device and the peripheral device indicate that they
are ready for a transfer, one data point is latched. Burst mode can
transfer data at high rates, particularly over short cables.
Comparing Protocols
Table3-1 shows similarities and differences among the 6533 device
handshaking modes. Asynchronous protocols use only the ACK and
REQ signals. Burst mode, a synchronous protocol, uses the ACK, REQ,
and PCLK signals. The PCLK line shares a clock signal between the
6533 device and the peripheral device.
Table3-1 shows peak handshaking rates for typical cable lengths. The
peak rates give an upper limit, deriving from the pulse widths and other
timing specifications of the handshaking protocol. Your actual
maximum rate depends on many factors; see the Transfer Rates section
in this chapter.
Table3-1 also shows whether the ACK and REQ signals are active
high, active low, or programmable polarity. The table shows whether
the leading or trailing edge of a REQ pulse initiates a data transfer. The
table also describes the effect on each protocol of setting a
programmable delay. See Chapter5, Signal Timing, for timing details.
The table also shows complementary protocols with which the protocol
can communicate, assuming that you choose complementary settings
for any options the two protocols offer. For example, a 6533 device in
8255 emulation mode can communicate with a 6533 device in long
pulse mode, if you select ACK and REQ to be active low.