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DIO 6533 User Manual I-4
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National Instruments Corporation
purpose and use, 3-9
timing specifications, 5-11 to 5-13
input timing (figure), 5-12
output timing (figure), 5-13
line polarities, controlling, 3-13
long-pulse mode, 5-19 to 5-22
input (figure), 5-19
output (figure), 5-20
purpose and use, 3-9
timing specifications
input timing (figure), 5-21
output timing (figure), 5-22
M
manual. See documentation.
message generation, 3-8
N
National Instruments application software, 1-4
to 1-5
NI-DAQ driver software, 1-5 to 1-6
noise, minimizing, 4-14 to 4-15
P
pattern generation
change detection, 3-7 to 3-8
definition, 3-6
message generation, 3-8
overview, 3-5 to 3-6
pattern-detection triggers, 3-6 to 3-7
example, 3-7
specifying parameters to
pattern-detection circuit, 3-6 to 3-7
pattern generation timing, 5-1 to 5-4
example (figure), 5-1
overview, 5-1
request timing, 5-2 to 5-3
external requests, 5-2 to 5-3
internal requests, 5-2
trigger timing, 5-3 to 5-4
PC AT devices. See AT device configuration.
PCI-DIO-32HS
block diagram, 3-2
configuration, 2-4
installation, 2-1 to 2-2
overview, 1-1
PCLK<1..2> signal
control signal summary (table), 4-7
description (table), 4-4
peripheral device, 3-5
physical specifications, A-8
pin assignments
I/O connector (figure), 4-2
optional adapter (figure), B-2
pins used by PXI-6533 device (table), 1-3
Plug and Play mode, configuring, 2-5
polarity, of signals, 4-6
power connections, 4-14
power requirement specifications, A-8
pull-up and pull-down connections, 4-13 to
4-14
pull-up/pull-down characteristics, 4-6
pulses
leading-edge pulse, 3-9
long pulse, 3-9
trailing-edge pulse, 3-9
PXI-6533
block diagram, 3-2
configuration, 2-4
installation, 2-2 to 2-3
overview, 1-1
pins used by (table), 1-3
R
register-level programming, 1-6
REQ<1..2> signal