National Instruments DIO 6533 Switch User Manual


 
Chapter 5 Signal Timing
© National Instruments Corporation 5-9 DIO 6533 User Manual
Other Asynchronous Modes
Besides 8255-compatible mode, the 6533 device supports several other
asynchronous handshaking protocols: level-ACK mode, leading-edge
mode, long-pulse mode, and trailing-edge mode. These handshaking
modes are compatible with the handshaking modes of the National
Instruments AT-DIO-32F device.
Each of these modes offers the following options:
Polarity of the ACK and REQ signals. The diagrams show
active-high signals.
A programmable delay, from 0 to 700 ns, programmable in
increments of 100 ns. You can use the programmable delay to
reduce handshaking speed for slow peripheral devices. A delay
increases the duration of each transfer. The location of the delay in
the handshaking sequence differs from protocol to protocol. In
addition, a delay increases the minimum spacing between
consecutive transfers.
Request-edge latching. With request-edge latching enabled, in
input mode, the 6533 device latches data in from the I/O connector
on the REQ edge before reading the data. In output mode, after
writing the data, the 6533 device latches data out of the I/O
connector on the REQ edge. Which edge of REQ is used (rising or
falling) depends on the handshaking mode and the REQ polarity.
Level-ACK Mode
In level-ACK mode, the 6533 device asserts the ACK signal when ready
for a transfer and holds the ACK signal level until an active-going edge
occurs on the REQ line. After the REQ edge occurs, the 6533 device
deasserts the ACK signal until ready for another transfer.
Input
In input mode, the 6533 device asserts the ACK signal when ready to
accept data. The peripheral device can then strobe data into the 6533
device by asserting the REQ signal. The active-going REQ signal edge
deasserts the ACK signal and causes the 6533 device to latch input data.
Afterward, the 6533 device reasserts the ACK signal when ready for
another input.
To slow down the handshake, you can specify a data-settling delay to
occur before the ACK signal.