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Rev.2.00 Nov 28, 2005 page 327 of 378
REJ09B0124-0200
M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 22.20 Timing Diagram (8)
Read timing
Write timing
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting, external area access and multiplexed bus selection)
BCLK
CSi
ALE
RD
ADi
/DBi
ADi
BHE
BCLK
CSi
ALE
ADi
/DBi
tcyc
t
d(BCLK-AD)
40ns.max
tcyc
Data output
t
h(BCLK-CS)
6ns.min
t
d(BCLK-CS)
40ns.max
t
d(BCLK-ALE)
40ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
40ns.max
t
h(BCLK-RD)
0ns.min
t
SU(DB-RD)
50ns.min
t
h(RD-DB)
0ns.min
t
h(RD-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-AD)
4ns.min
t
d(BCLK-CS)
40ns.max
t
d(BCLK-AD)
40ns.max
t
h(BCLK-DB)
4ns.min
t
h(BCLK-WR)
0ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
t
d(BCLK-ALE)
40ns.max
t
d(BCLK-WR)
40ns.max
t
-4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
Data input
Address
Address
ADi
BHE
WR, WRL
WRH
t
d(AD-ALE)
(0.5 ✕ tcyc-40)ns.min
t
d(AD-RD)
0ns.min
t
dZ(RD-AD)
8ns.max
t
ac3(RD-DB)
t
d(BCLK-DB)
50ns.max
(0.5 ✕ tcyc-10)ns.min
t
h(WR-CS)
t
d(AD-WR)
0ns.min
t
h(RD-CS)
(0.5 ✕ tcyc-10)ns.min
t
d(AD-ALE)
(0.5 ✕ tcyc-40)ns.min
(2.5 ✕ tcyc-60)ns.max
(no multiplex)
(no multiplex)
tcyc =
1
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : V
IL
= 0.6 V, V
IH
= 2.7 V
Output timing voltage : V
OL
= 1.65 V, V
OH
= 1.65 V
t
d(DB-WR)
(2.5 ✕ tcyc-50)ns.min
h(BCLK-ALE)
(0.5 ✕ tcyc-15)ns.min
t
h(ALE-AD)
VCC = 3.3V