Filter
Top Products
Rev.2.00 Nov 28, 2005 page 55 of 378
REJ09B0124-0200
M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus
Under development
This document is under development and its contents are subject to change.
Figure 7.8 Typical Bus Timings Using Software Wait (2)
Address
Output
Input
Address
BCLK
CS
Write signal
Read signal
Data bus
Address bus
(1) Separate bus, 3-wait setting
Address bus/
Data bus
Address
Address
Data output
Address
Address
Input
ALE
BCLK
CS
Write signal
Read signal
Address bus
(2)Multiplexed bus, 1- or 2-wait setting
Address
Data output
Address
Address
Input
Read signal
Write signal
Address bus/
Data bus
CS
Address bus
ALE
Address
BCLK
(3)Multiplexed bus, 3-wait setting
NOTE:
1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and
write cycles in succession.
Bus cycle
(1)
Bus cycle
(1)
Bus cycle
(1)
Bus cycle
(1)
Bus cycle
(1)
Bus cycle
(1)