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Rev.2.00 Nov 28, 2005 page 52 of 378
REJ09B0124-0200
M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus
Under development
This document is under development and its contents are subject to change.
7.2.10 Software Wait
Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits
in the CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is
always accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. See
Table 7.8 Bit and Bus Cycle Related to Software Wait for details.
________
To use the RDY signal, set the corresponding CS3W to CS0W bit to “0” (with wait state). Figure 7.6 shows
the CSE register. Table 7.8 shows the software wait related bits and bus cycles. Figures 7.7 and 7.8 show
the typical bus timings using software wait.
7.2.9 External Bus Status When Internal Area Accessed
Table 7.7 shows the external bus status when the internal area is accessed.
Table 7.7 External Bus Status When Internal Area Accessed
Figure 7.6 CSE Register
Item SFR Accessed Internal ROM, Internal RAM Accessed
A0 to A19 Address output Maintain status before accessed address
of external area or SFR
D0 to D15 When read High-impedance High-impedance
When write Output data Undefined
_____ ______ ________ _________
RD, WR, WRL, WRH
_____ ______ _________ __________
RD, WR, WRL, WRH output Output “H”
________
BHE
________
BHE output Maintain status before accessed status of
external area or SFR
_______ _______
CS0 to CS3 Output “H” Output “H”
ALE Output “L” Output “L”
CS0 Wait Expansion Bit
(1)
CS1 Wait Expansion Bit
(1)
CS2 Wait Expansion Bit
(1)
CS3 Wait Expansion Bit
(1)
0 0 : 1 wait
0 1 : 2 waits
1 0 : 3 waits
1 1 : Do not set a value
b1 b0
0 0 : 1 wait
0 1 : 2 waits
1 0 : 3 waits
1 1 : Do not set a value
b3 b2
0 0 : 1 wait
0 1 : 2 waits
1 0 : 3 waits
1 1 : Do not set a value
b5 b4
0 0 : 1 wait
0 1 : 2 waits
1 0 : 3 waits
1 1 : Do not set a value
b7 b6
Bit Name Function
Bit Symbol
RW
Chip Select Expansion Control Register
(2)
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
RW
RW
RW
RW
RW
RW
Symbol Address After Reset
CSE 001Bh 00h
CSE00W
CSE01W
CSE10W
CSE11W
CS20WE
CSE21W
CSE30W
CSE31W
NOTES:
1. Set the CSiW bit (i = 0 to 3) in the CSR register to "0" (with wait state) before writing to the CSEi1W to CSEi0W
bits. If the CSiW bit needs to be set to "1" (without wait state), set the CSEi1W to CSEi0W bits to "00b" before
setting it.
2. Not available this register in T/V-ver..