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Rev.2.00 Nov 28, 2005 page 54 of 378
REJ09B0124-0200
M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus
Under development
This document is under development and its contents are subject to change.
Figure 7.7 Typical Bus Timings Using Software Wait (1)
NOTE:
1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and
write cycles in succession.
Output
Input
Address
Address
BCLK
Read signal
Write signal
Data bus
Address bus
CS
(2) Separate bus, 1-wait setting
BCLK
Read signal
Write signal
Data bus
Address bus
Address
Address
Bus cycle
(1)
Output
Input
Bus cycle
(1)
Bus cycle
(1)
Bus cycle
(1)
CS
(1) Separate bus, No wait setting
Output
Address
Address
Input
BCLK
CS
Read signal
Write signal
Data bus
Address bus
(3) Separate bus, 2-wait setting
Bus cycle
(1)
Bus cycle
(1)