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Rev.2.00 Nov 28, 2005 page 362 of 378
REJ09B0124-0200
M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution
Under development
This document is under development and its contents are subject to change.
23.14 CAN Module
23.14.1 Reading CiSTR Register (i = 0, 1)
The CAN module on the M16C/6N Group (M16C/6NK, M16C/6NM) updates the status of the CiSTR
register in a certain period. When the CPU and the CAN module access to the CiSTR register at the same
time, the CPU has the access priority; the access from the CAN module is disabled. Consequently, when
the updating period of the CAN module matches the access period from the CPU, the status of the CAN
module cannot be updated. (See Figure 23.5 When Updating Period of CAN Module Matches Access
Period from CPU.)
Accordingly, be careful about the following points so that the access period from the CPU should not
match the updating period of the CAN module:
(a) There should be a wait time of 3fCAN or longer (see Table 23.3 CAN Module Status Updating Period)
before the CPU reads the CiSTR register. (See Figure 23.6 With a Wait Time of 3fCAN Before CPU
Read.)
(b) When the CPU polls the CiSTR register, the polling period must be 3fCAN or longer. (See Figure 23.7
When Polling Period of CPU is 3fCAN or Longer.)
Table 23.3 CAN Module Status Updating Period
3fCAN Period = 3 ✕ XIN (Original Oscillation Period) ✕ Division Value of CAN Clock (CCLK)
(Example 1) Condition XIN 16 MHz CCLK: Divided by 1 3fCAN period = 3 ✕ 62.5 ns ✕ 1 = 187.5 ns
(Example 2) Condition XIN 16 MHz CCLK: Divided by 2 3fCAN period = 3 ✕ 62.5 ns ✕ 2 = 375 ns
(Example 3) Condition XIN 16 MHz CCLK: Divided by 4 3fCAN period = 3 ✕ 62.5 ns ✕ 4 = 750 ns
(Example 4) Condition XIN 16 MHz CCLK: Divided by 8 3fCAN period = 3 ✕ 62.5 ns ✕ 8 = 1.5 µs
(Example 5) Condition XIN 16 MHz CCLK: Divided by 16 3fCAN period = 3 ✕ 62.5 ns ✕ 16 = 3 µs