Rev.2.00 Nov 28, 2005 page 48 of 378
REJ09B0124-0200
M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus
Under development
This document is under development and its contents are subject to change.
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Table 7.4 Operation of RD, WR and BHE Signals
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Table 7.3 Operation of RD, WRL and WRH Signals
7.2.4 Read and Write Signals
_____
When the data bus is 16-bit width, the read and write signals can be chosen to be a combination of RD,
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WR and BHE or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When
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the data bus is 8-bit width, use a combination of RD, WR and BHE.
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Table 7.3 shows the operation of RD, WRL, and WRH signals. Table 7.4 shows the operation of RD, WR,
________
and BHE signals.
7.2.5 ALE Signal
The ALE signal latches the address when accessing the multiplexed bus space. Latch the address when
the ALE signal falls. Figure 7.3 shows the ALE signal, address bus and data bus.
Figure 7.3 ALE Signal, Address Bus, Data Bus
L
H
L
H
L
H
L
H
Data Bus Width
_____
RD
________
WRL
_________
WRH Status of External Data Bus
16 Bits
(BYTE pin
input = L)
L
H
H
H
H
L
H
L
H
H
L
L
Read data
Write 1 byte of data to an even address
Write 1 byte of data to an odd address
Write data to both even and odd addresses
Data Bus Width
_____
RD
______
WR
________
BHE
Status of External Data Bus
16 Bits
(BYTE pin
input = L)
8 Bits
(BYTE pin input = H)
H
L
H
L
H
L
H
L
L
L
H
H
L
L
Not used
Not used
Write 1 byte of data to an odd address
Read 1 byte of data from an odd address
Write 1 byte of data to an even address
Read 1 byte of data from an even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
H
H
L
L
L
L
H to L
H to L
A0
Address Data
Address
(1)
Address Data
Address
Address
NOTE:
1. If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.
A0/D0 to A7/D7
A8 to A19
ALE
A1/D0 to A8/D7
A9 to A19
A0
ALE
When BYTE pin input = H When BYTE pin input = L