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Rev.2.00 Nov 28, 2005 page 47 of 378
REJ09B0124-0200
M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus
Under development
This document is under development and its contents are subject to change.
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Figure 7.2 Example of Address Bus and CSi Signal Output
NOTE:
1. These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle may be
extended more than two cycles depending on a combination of these examples.
Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3 (not including i, however)
To access the external area indicated by CSj in the next cycle
after accessing the external area indicated by CSi.
The address bus and the chip select signal both change state
between these two cycles.
Example 2
To access the internal ROM or internal RAM in the next cycle
after accessing the external area indicated by CSi.
The chip select signal changes state but the address bus
does not change state.
Example 1
BCLK
Read signal
Data bus
Address bus
CSi
Access to the external
area indicated by CSi
Access to the external
area indicated by CSj
Address
Data
CSj
Data
BCLK
Read signal
Data bus
Address bus
CSi
Access to the external
area indicated by CSi
Access to the internal
ROM or internal RAM
Address
Data
Address
Example 4
Not to access any area (nor instruction prefetch generated)
in the next cycle after accessing the external area indicated
by CSi.
Neither the address bus nor the chip select signal changes
state between these two cycles.
To access the external area indicated by CSi in the next cycle
after accessing the external area indicated by the same CSi.
The address bus changes state but the chip select signal
does not change state.
Example 3
BCLK
Read signal
Data bus
Address bus
CSi
Access to the external
area indicated by CSi
Access to the same
external area
Address
Data Data
BCLK
Read signal
CSi
Access to the external
area indicated by CSi
No access
Address
Data
Address
Data bus
Address bus