Filter
Top Products
Rev.2.00 Nov 28, 2005 page 41 of 378
REJ09B0124-0200
M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode
Under development
This document is under development and its contents are subject to change.
Figure 6.2 PM1 Register
Symbol Address After reset
PM1 0005h 00001000b
PM17
PM13
PM12
PM10
PM11
-
(b6-b4)
CS2 Area Switch Bit
(Data Block Enable Bit)
(2)
Port P3_7 to P3_4 Function
Select Bit
(3)
Watchdog Timer Function
Select Bit
RW
RW
RW
RW
RW
RW
RW
0 : No wait state
1 : With wait state (1 wait)
Set to "0"
0 : Watchdog timer interrupt
1 : Watchdog timer reset
(4)
0 :
08000h to 26FFFh
(Block A disable)
1 :
10000h to 26FFFh
(Block A enable)
0 : Address output
1 : Port function
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
2. For the mask ROM version, this bit must be set to "0".
For the flash memory version, the PM10 bit also controls block A by enabling or disabling it. When the PM10
bit is set to "1", 0F000h to 0FFFFh (block A) can be used as internal ROM area.
In addition, the PM10 bit is automatically set to "1" when the FMR01 bit in the FMR0 register is "1" (CPU rewrite
mode).
3. Effective when the PM01 to PM00 bits are set to "01b" (memory expansion mode) or "11b" (microprocessor mode).
* Not available memory expansion and microprocessor modes in T/V-ver.. This bit is reserved bit in T/V-ver.,
and set to "0".
4. The PM12 bit is set to "1" by writing a "1" in a program. (Writing a "0" has no effect.)
5. Be sure to set this bit to "0" except for products with internal ROM area over 192 Kbytes.
The PM13 bit is automatically set to "1" when the FMR01 bit in the FMR0 register is "1" (CPU rewrite mode).
6. When the PM17 bit is set to "1" (with wait state), one wait state is inserted when accessing the internal RAM
or internal ROM.
When the PM17 bit is set to "1" and accesses an external area, set the CSiW bit (i = 0 to 3) in the CSR register
to "0" (with wait state).
7. The access area is changed by the PM13 bit as listed in the table below.
* External area is not available in T/V-ver..
Bit name Function
Internal Reserved Area
Expansion Bit
(5)
Reserved Bit
Wait Bit
(6)
Processor Mode Register 1
(1)
000
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
See NOTE 7
Access area PM13 = 0 PM13 = 1
Internal
External
RAM
ROM
Up to addresses 00400h to 03FFFh (15 Kbytes)
Up to addresses D0000h to FFFFFh (192 Kbytes)
Addresses 04000h to 07FFFh are usable
Addresses 80000h to CFFFFh are usable
The entire area is usable
The entire area is usable
Addresses 04000h to 07FFFh are reserved
Addresses 80000h to CFFFFh are reserved
(Memory expansion mode)