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TMS320C6712D
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PLL and PLL controller
The TMS320C6712D includes a PLL and a flexible PLL controller peripheral consisting of a prescaler (D0) and
four dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for different
parts of the system (i.e., DSP core, Peripheral Data Bus, External Memory Interface, McASP, and other
peripherals). Figure 8 illustrates the PLL, the PLL controller, and the clock generator logic.
CLKIN
CLKOUT3
For Use
in System
/1, /2,
..., /32
..., /32
/1, /2,
PLL
x4 to x25
PLLEN (PLL_CSR.[0])
..., /32
/1, /2,
/1, /2,
..., /32
/1, /2,
..., /32
(DSP Core)
SYSCLK1
(Peripherals)
SYSCLK2
ECLKIN
EKSRC Bit
(DEVCFG.[4])
EMIF
†
Dividers D1 and D2 must never be disabled. Never write a “0” to the D1EN or D2EN bits in the PLLDIV1 and PLLDIV2 registers.
SYSCLK3
CLKMODE0
(EMIF Clock Input)
C6712D DSP
PLLOUT
PLLREF
DIVIDER D0
OSCDIV1
DIVIDER D1
†
DIVIDER D2
†
DIVIDER D3
ECLKOUT
1
0
1 0
1
0
PLLHV
C2C1
EMI filter
+3.3 V
10 µF 0.1 µF
D0EN (PLLDIV0.[15])
ENA
ENA
OD1EN (OSCDIV1.[15])
ENAENA
ENA
D1EN (PLLDIV1.[15])
ENAD2EN (PLLDIV2.[15])
ENA
D3EN (PLLDIV3.[15])
Reserved
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C67x DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV
DD
.
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure 8. PLL and Clock Generator Logic