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TMS320C6712D
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
81
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOLD/HOLDA TIMING
timing requirements for the HOLD
/HOLDA cycles
†
(see Figure 37)
NO.
−150
UNIT
NO.
MIN MAX
UNIT
3 t
h(HOLDAL-HOLDL)
Hold time, HOLD low after HOLDA low E ns
†
E = ECLKIN period in ns
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles
†‡
(see Figure 37)
NO.
PARAMETER
−150
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 t
d(HOLDL-EMHZ)
Delay time, HOLD low to EMIF Bus high impedance 2E
§
ns
2 t
d(EMHZ-HOLDAL)
Delay time, EMIF Bus high impedance to HOLDA low 0 2E ns
4 t
d(HOLDH-EMLZ)
Delay time, HOLD high to EMIF Bus low impedance 2E 7E ns
5 t
d(EMLZ-HOLDAH)
Delay time, EMIF Bus low impedance to HOLDA high 0 2E ns
†
E = ECLKIN period in ns
‡
EMIF Bus consists of CE[3:0]
, BE[1:0], ED[15:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
§
All pending EMIF transactions are allowed to complete before HOLDA
is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
HOLD
HOLDA
EMIF Bus
†
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
C6712D C6712D
1
3
25
4
†
EMIF Bus consists of CE[3:0]
, BE[1:0], ED[15:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
Figure 37. HOLD/HOLDA Timing