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TMS320C6712D
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
73
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles
†
(see Figure 28)
NO.
−150
UNIT
NO.
MIN MAX
UNIT
6 t
su(EDV-EKOH)
Setup time, read EDx valid before ECLKOUT high 1.5 ns
7 t
h(EKOH-EDV)
Hold time, read EDx valid after ECLKOUT high 2.5 ns
†
The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but
random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles
†‡
(see Figure 28 and Figure 29)
NO.
PARAMETER
−150
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 t
d(EKOH-CEV)
Delay time, ECLKOUT high to CEx valid 1.2 7 ns
2 t
d(EKOH-BEV)
Delay time, ECLKOUT high to BEx valid 7 ns
3 t
d(EKOH-BEIV)
Delay time, ECLKOUT high to BEx invalid 1.2 ns
4 t
d(EKOH-EAV)
Delay time, ECLKOUT high to EAx valid 7 ns
5 t
d(EKOH-EAIV)
Delay time, ECLKOUT high to EAx invalid 1.2 ns
8 t
d(EKOH-ADSV)
Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 1.2 7 ns
9 t
d(EKOH-OEV)
Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 1.2 7 ns
10 t
d(EKOH-EDV)
Delay time, ECLKOUT high to EDx valid 7 ns
11 t
d(EKOH-EDIV)
Delay time, ECLKOUT high to EDx invalid 1.2 ns
12 t
d(EKOH-WEV)
Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 1.2 7 ns
†
The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but
random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
‡
ARE
/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.