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Intel
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IXP45X and Intel
®
IXP46X Product Line of Network Processors—General Hardware
Design Considerations
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
HDD February 2007
20 Document Number: 305261; Revision: 004
3.2.2 DDR SDRAM Memory Interface
The IXP45X/IXP46X network processors support compatible DDR-266 SDRAM, 8- and
16-bit wide devices, with a total bus width of 32 bits. Only 32-bit-wide accesses are
supported.
The maximum supported memory is 1 Gbyte, configured by enabling both physical
banks of DDR-266 SDRAM devices. Each bank can be composed of four 1-Gbit (32 Mbit
X 8 X 4) devices and use one chip-selects per bank. The minimum supported memory
is 32 Mbyte, configured by enabling a single physical bank of DDR-266 SDRAM devices.
The bank would consist of two 128-Mbit (2 Mbit X 16 X 4) devices and using a single
chip-select.
All supported memory configurations are listed in Table 28 on page 78. Remember that
these are all non-buffer devices, as the IXP45X/IXP46X network processors only
support non-buffer memory devices.
For a complete description on how the IXP45X/IXP46X network processors interface to
DDR SDRAM, see Chapter 7.0, “DDR-SDRAM”.
3.2.3 DDR SDRAM Initialization
For instructions on DDR SDRAM initialization, refer to the Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors Developer’s Manual and its section titled
“DDR SDRAM Initialization.”
3.3 Expansion Bus
The Expansion Bus of the IXP45X/IXP46X network processors is specifically designed
for compatibility with Intel- and Motorola*-style microprocessor interfaces and Texas
Instruments* DSP standard Host-Port Interfaces* (HPI).
The expansion bus controller includes a 25-bit address bus and a 32-bit wide data path,
running at a maximum speed of 80 MHz from an external clock oscillator. The bus can
be configure to support the following target devices:
The expansion bus controller also has an arbiter that supports up to four external
devices that can master the expansion bus. External masters can be used to access
external slave devices that reside on the expansion bus, including access to internal
memory mapped regions within the IXP45X/IXP46X network processors.
All supported modes are seamless and no additional glue logic is required. Other cycle
types may be supported by configuring the Timing and Control Register for Chip Select.
Applications having less than 32 data bits may connect to less than the full 32 bits.
Devices with wider than 32-bit data bus are not supported. A total of eight chip selects
are supported with an address space of up to 32 Mbytes per chip select.
• Intel multiplexed • Intel non-multiplexed
•Intel StrataFlash
®
• Synchronous Intel StrataFlash
®
Memory
• Micron* Flow-Through ZBT • Motorola multiplexed
• Motorola non multiplexed • Texas Instruments* Host Port Interface
(HPI)