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Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
February 2007 HDD
Document Number: 305261, Revision: 004 77
DDR-SDRAM—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Besides assigning clock signals (DDRI_CK and DDRI_CK_N) to the memory devices,
there are two more requirements, one implemented in hardware (termination) and the
other implemented in software (configuration), these requirements are explained as
follow:
• It is recommended to properly terminate the clock output signals by the Thevenin
terminations scheme as shown in Figure 37. Simulation is recommended for cases
that required deviation from the recommended topology, which include series
termination and trace impedance.
• It is required to tune the drive strength of the clock driver to properly drive clocks
out to loads of one or two memory devices, terminated with Thevenins termination
scheme. Follow the recommendations described in Section 7.1.6, “Resistive
Compensation Register (Rcomp)” on page 88.
Note that when simulating, the IBIS model representation of signals DDRI_CK[2:0] and
DDRI_CK_N[2:0] has been created for the new Rcomp settings described in Section
7.1.6, “Resistive Compensation Register (Rcomp)” on page 88