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Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
February 2007 HDD
Document Number: 305261, Revision: 004 3
Contents—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Contents
1.0 Introduction ..............................................................................................................9
1.1 Content Overview................................................................................................9
1.2 Related Documentation ...................................................................................... 10
1.3 Acronyms and Abbreviations............................................................................... 11
1.4 Overview ......................................................................................................... 11
1.5 Typical Applications ........................................................................................... 14
2.0 System Architecture ................................................................................................ 15
2.1 System Architecture Description.......................................................................... 15
2.2 System Memory Map ......................................................................................... 15
3.0 General Hardware Design Considerations ................................................................ 17
3.1 Soft Fusible Features ......................................................................................... 17
3.2 DDR-266 SDRAM Interface ................................................................................. 18
3.2.1 Signal Interface ..................................................................................... 18
3.2.2 DDR SDRAM Memory Interface................................................................. 20
3.2.3 DDR SDRAM Initialization ........................................................................ 20
3.3 Expansion Bus .................................................................................................. 20
3.3.1 Signal Interface ..................................................................................... 21
3.3.2 Reset Configuration Straps ...................................................................... 21
3.3.3 8-Bit Device Interface ............................................................................. 23
3.3.4 16-Bit Device Interface ........................................................................... 23
3.3.5 32-Bit Device Interface ........................................................................... 24
3.3.6 Flash Interface....................................................................................... 27
3.3.7 SRAM Interface...................................................................................... 28
3.3.8 Design Notes ......................................................................................... 28
3.4 UART Interface ................................................................................................. 28
3.4.1 Signal Interface ..................................................................................... 29
3.5 MII/SMII Interface ............................................................................................ 30
3.5.1 Signal Interface MII................................................................................ 31
3.5.2 Device Connection, MII ........................................................................... 33
3.5.3 Signal Interface, SMII............................................................................. 34
3.5.4 Device Connection, SMII ......................................................................... 35
3.6 GPIO Interface.................................................................................................. 35
3.6.1 Signal Interface ..................................................................................... 36
3.6.2 Design Notes ......................................................................................... 36
3.7 I
2
C Interface .................................................................................................... 37
3.7.1 Signal Interface ..................................................................................... 37
3.7.2 Device Connection.................................................................................. 37
3.8 USB Interface ................................................................................................... 38
3.8.1 Signal Interface ..................................................................................... 39
3.8.2 Device Connection.................................................................................. 40
3.9 UTOPIA Level 2 Interface ................................................................................... 41
3.9.1 Signal Interface ..................................................................................... 42
3.9.2 Device Connection.................................................................................. 42
3.10 HSS Interface ................................................................................................... 43
3.10.1 Signal Interface ..................................................................................... 44
3.10.2 Device Connection.................................................................................. 46
3.11 SSP Interface ................................................................................................... 46
3.11.1 Signal Interface ..................................................................................... 47
3.11.2 Device Connection.................................................................................. 47
3.12 PCI Interface .................................................................................................... 48