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Specifications CBI/CGI Technical Reference
Chassis Plans1-8
(L1) instruction cache and 16K L1 data cache. These cache arrays run at the full speed
of the processor core.
For Celeron processors, a 128K unified, non-blocking second level (L2) cache improves
performance by reducing the average memory access time and providing fast access to
recently used instructions and data.
DRAM M
EMORY The DRAM interface consists of two dual in-line memory module (DIMM) sockets and
supports auto detection of memory up to 512MB of Synchronous DRAM (SDRAM) for
the 440BX or up to 1GB of SDRAM for the 440GX. Minimum memory size is 8MB.
The System BIOS automatically detects memory type, size and speed.
The SBC uses industry standard 64-bit or 72-bit wide gold finger DIMM SDRAM
modules in two 168-pin DIMM sockets.
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NOTE: Memory can be installed in one or both DIMM sockets. If only one DIMM
module is used, it must be populated in the top DIMM socket (Bank 1 - BK1). If two
modules are used, they must be the same DIMM type, but may be different sizes (see
table below). EDO DIMMs are not supported. All DIMMs must have gold contacts.
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The SBC supports DIMM memory modules which are PC-100 compliant and have the
following features:
• 168-pin DIMMs with gold-plated contacts
• 100MHz SDRAM
• Non-ECC (64-bit) or ECC (72-bit) memory
• 3.3 volt
• Single or double-sided DIMMs in the sizes listed below
• Buffered or Registered configuration
The following DIMM sizes are supported:
All memory components and DIMMs used with the SBC must be PC-100 compliant,
which means that they comply with Intel's PC SDRAM specifications. These include the
PC SDRAM Specification (memory component specific), the PC Unbuffered DIMM
DIMM
Size
DIMM Type Non-ECC ECC
8MB
16MB
32MB
64MB
128MB
256MB
512MB
Unbuffered
Unbuffered
Unbuffered
Unbuffered
Unbuffered
Registered
Registered
1M x 64
2M x 64
4M x 64
8M x 64
16M x 64
32M x 64
64M x 64
1M x 72
2M x 72
4M x 72
8M x 72
16M x 72
32M x 72
64M x 72 *
* CGI models only