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SpecificationsCBI/CGI Technical Reference
Chassis Plans 1-11
PCI ENHANCED
IDE U
LTRA
DMA/33
I
NTERFACE (DUAL)
Dual high performance PCI Bus Master EIDE interfaces are capable of supporting two
IDE Type 4 disk drives each in a master/slave configuration. The interface supports
Ultra DMA/33 with synchronous DMA mode transfers up to 33MB per second.
F
LOPPY DRIVE
I
NTERFACE
The SBC supports two floppy disk drives. Drives can be 360K to 2.88MB, in any
combination.
S
ERIAL INTERFACE Two high-speed FIFO (16C550) serial ports with independently programmable baud
rates are supported. The IRQ for each serial port has BIOS selectable addressing.
E
NHANCED
P
ARALLEL
I
NTERFACE
The SBC provides a PC/AT compatible bidirectional parallel port and supports enhanced
parallel port (EPP) mode and extended capabilities port (ECP) mode. The ECP mode is
IEEE 1284 compliant. The IRQ for the parallel port has BIOS selectable addressing.
PS/2 M
OUSE
I
NTERFACE
The SBC is compatible with a PS/2-type mouse. The mouse connection can be made by
using either the PS/2 mouse header or the bracket mounted PS/2 mouse mini DIN
connector. Mouse voltage is protected by a self-resetting fuse.
K
EYBOARD
I
NTERFACE
The SBC is compatible with an AT-type keyboard. The keyboard connection can be
made by using either the keyboard header or the bracket mounted keyboard mini DIN
connector. Keyboard voltage is protected by a self-resetting fuse.
W
ATCHDOG TIMER The watchdog timer is a hardware timer which resets the SBC if the timer is not
refreshed by software periodically. The timer is typically used to restart a system in
which an application becomes hung on an external event. When the application is hung,
it no longer refreshes the timer. The watchdog timer then times out and resets the SBC.
The watchdog timer has two levels of enable. First, the watchdog timer jumper must be
moved to the "enabled" position, which puts the watchdog timer under software control.
The second level involves software control of the watchdog's timer retriggering. Bit 6 of
the 82371EB GPOREG register at I/O address 437H must be set to a zero (0), which
blocks the triggering clock to the watchdog timer circuit, thus scheduling a hardware
reset in about 1.5 seconds.
To refresh the watchdog timer, the software in the application toggles bit 6 of the
GPOREG register. First the bit must be set to a one (1) to clear the watchdog timer
delay; then it must be set to a zero (0), which schedules a system reset in 1.5 seconds.
Toggling bit 6 of the GPOREG must occur within a period of less than 1.5 seconds to
insure that a system reset is not issued.
A set of watchdog timer software code and sample programs are available from
Technical Support.
P
OWER FAIL
DETECTION
A hardware reset is issued when on-board +5V voltage drops below 4.75 volts. In
addition, if the 3.3V Monitor jumper (JU15) is enabled, a reset is issued if 3.3V is below
tolerance. (See the Configuration Jumpers section later in this chapter.)