Filter
Top Products
ISA/PCI Reference CBI/CGI Technical Reference
Chassis Plans2-14
PCI LOCAL BUS
S
IGNAL
D
ESCRIPTIONS
The PCI Local Bus signals are described below and may be categorized into the
following functional groups:
• System Pins
• Address and Data Pins
• Interface Control Pins
• Arbitration Pins (Bus Masters Only)
• Error Reporting Pins
• Interrupt Pins (Optional)
• Cache Support Pins (Optional)
• 64-Bit Bus Extension Pins (Optional)
• JTAG/Boundary Scan Pins (Optional)
A # symbol at the end of a signal name indicates that the active state occurs when the
signal is at a low voltage. When the # symbol is absent, the signal is active at a high
voltage.
The following are descriptions of the PCI Local Bus signals.
ACK64# (optional)
Acknowledge 64-bit Transfer, when actively driven by the device that has positively decoded its
address as the target of the current access, indicates the target is willing to transfer data using
64bits. ACK64# has the same timing as DEVSEL#.
AD[31::00]
Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an
address phase followed by one or more data phases. During the address phase, AD[31::00]
contain a physical address (32 bits). During data phases, AD[07::00] contain the least signif-
icant byte (lsb) and AD[31::24] contain the most significant byte (msb).
AD[63::32] (optional)
Address and Data are multiplexed on the same pins and provide 32additional bits. During an
address phase (when using the DAC command and when REQ64# is asserted), the upper
32bits of a 64-bit address are transferred; otherwise, these bits are reserved but are stable and
indeterminate. During a data phase, an additional 32bits of data are transferred when REQ64#
and ACK64# are both asserted.
C/BE[3::0]#
Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address
phase of a transaction, these pins define the bus command; during the data phase they are
used as byte enables. The byte enables are valid for the entire data phase and determine
which byte lanes carry meaningful data. C/BE0# applies to byte0 (lsb) and C/BE3# applies to
byte 3 (msb).