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ISA/PCI Reference CBI/CGI Technical Reference
Chassis Plans2-4
IO16# (I)
I/O 16-bit Chip Select (IO16#) signals the system board that the present data transfer is a 16-bit,
1 wait-state, I/O cycle. It is derived from an address decode. IO16# is active low and should be
driven with an open collector or tri-state driver capable of sinking 20 mAmps.
IOCHK# (I)
I/O Channel Check (IOCHK#) provides the system board with parity (error) information about
memory or devices on the I/O channel. When this signal is active, it indicates an uncorrectable
system error.
IORC# (I/O)
I/O Read (IORC#) instructs an I/O device to drive its data onto the data bus. It may be driven by
the system microprocessor or DMA controller, or by a microprocessor or DMA controller
resident on the I/O channel. This signal is active low.
IOWC# (I/O)
I/O Write (IOWC#) instructs an I/O device to read the data on the data bus. It may be driven by
any microprocessor or DMA controller in the system. This signal is active low.
IRQ[15::14], IRQ[12::9], IRQ[7::3] (I)
Interrupt Requests IRQ[15::14], IRQ[12::9] and IRQ[7::3] are used to signal the microprocessor
that an I/O device needs attention. The interrupt requests are prioritized, with IRQ[15::14] and
IRQ[12::9] having the highest priority (IRQ9 is the highest) and IRQ[7::3] having the lowest
priority (IRQ7 is the lowest). An interrupt request is generated when an IRQ line is raised from
low to high. The line must be held high until the microprocessor acknowledges the interrupt
request (Interrupt Service routine).
LA[23::17] (I/O)
These signals (unlatched) are used to address memory and I/O devices within the system.
They give the system up to 16MB of addressability. These signals are valid when BALE is high.
LA[23::17] are not latched during microprocessor cycles and therefore do not stay valid for the
whole cycle. Their purpose is to generate memory decodes for 1 wait-state memory cycles.
These decodes should be latched by I/O adapters on the falling edge of BALE. These signals
also may be driven by other microprocessors or DMA controllers that reside on the I/O channel.
M16# (I)
M16# Chip Select signals the system board if the present data transfer is a 1<N>wait-state, 16-
bit, memory cycle. It must be derived from the decode of LA[23::17]. M16# should be driven
with an open collector or tri-state driver capable of sinking 20 mAmps.
Master16# (I)
Master16# is used with a DRQ line to gain control of the system. A processor or DMA controller
on the I/O channel may issue a DRQ to a DMA channel in cascade mode and receive a DAK#.
Upon receiving the DAK#, an I/O microprocessor may pull Master16# low, which will allow it to
control the system address, data, and control lines (a condition known as tri-state). After
Master16# is low, the I/O microprocessor must wait one system clock period before driving the
address and data lines, and two clock periods before issuing a Read or Write command. If this
signal is held low for more than 15<N>microseconds, system memory may be lost because of a
lack of refresh.