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Advanced SetupCBI/CGI Technical Reference
Chassis Plans 5-15
Three options are available:
• None - No error checking or error reporting is done.
• EC - Multibit errors are detected and reported as parity errors. Single-bit
errors are corrected by the chipset. Corrected bits of data from memory are
not written back to DRAM system memory.
• ECC Hardware - Multibit errors are detected and reported as parity errors.
Single-bit errors are corrected by the chipset and are written back to DRAM
system memory.
If a soft (correctable) memory error occurs, writing the fixed data back to
DRAM system memory will resolve the problem. Most DRAM errors are
soft errors. If a hard (uncorrectable) error occurs, writing the fixed data
back to DRAM system memory does not solve the problem. In this case, the
second time the error occurs in the same location, a Parity Error is reported,
indicating an uncorrectable error.
DRAM Refresh Rate
This option specifies the interval between refresh signals to DRAM system memory.
Settings are in microseconds ("us").
The Setup screen displays the system option:
DRAM Refresh Rate 15.6 us
Available options are:
15.6 us
31.2 us
64.4 us
124.8 us
249.6 us
Memory Hole
This option may be used to specify an area in memory which cannot be addressed on the
ISA Bus.
The Setup screen displays the system option:
Memory Hole Disabled
Available options are:
Disabled
512KB-640KB
15MB-16MB