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ISA/PCI ReferenceCBI/CGI Technical Reference
Chassis Plans 2-9
PCI LOCAL BUS
S
IGNAL DEFINITION
The PCI interface requires a minimum of 47 pins for a target-only device and 49 pins for
a master to handle data and addressing, interface control, arbitration and system
functions. The diagram below shows the pins in functional groups, with required pins on
the left side and optional pins on the right side.
PCI Pin List
Required Pins:
Address & Data:
AD[31::00]
C/BE[3::0]#
PAR
Interface Control:
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
Error Reporting:
PERR#
SERR#
Arbitration
(masters only):
REQ#
GNT#
System:
CLK
RST#
Optional Pins:
64-bit Extension
AD[63::32]
C/BE[7::4]#
PAR64
REQ64#
ACK64#
Interface Control:
LOCK#
INTA#
INTB#
INTC#
INTD#
Cache Support:
SBO#
SDONE
JTAG (IEEE 1149.1):
TDI
TDO
TCK
TMS
TRST#
PCI
COMPLIANT
DEVICE